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CDCV857 Datasheet(PDF) 3 Page - Texas Instruments

Part # CDCV857
Description  2.5-V PHASE LOCK LOOP CLOCK DRIVER
PDF  1 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CDCV857 Datasheet(HTML) 3 Page - Texas Instruments

  CDCV857 Datasheet HTML 1Page - Texas Instruments  
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CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
3
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
17
Ground for 2.5
-V analog supply
AVDD
16
2.5
-V Analog supply
CLK, CLK
13, 14
I
Differential clock input
FBIN, FBIN
35, 36
I
Feedback differential clock input
FBOUT, FBOUT
32, 33
O
Feedback differential clock output
GND
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
Ground
PWRDWN
37
I
Output enable for Y and Y
VDDQ
4, 11, 12,
15, 21, 28,
34, 38, 45
2.5-V Supply
Y[0:9]
3, 5, 10,
20, 22, 27,
29, 39, 44,
46
O
Buffered output copies of input clock, CLK
Y[0:9]
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
O
Buffered output copies of input clock, CLK
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDDQ, AVDD
0.5 V to 3.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Notes 1 and 2)
–
0.5 V to VDDQ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2)
–
0.5 V to VDDQ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VDDQ)
±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VDDQ)
±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VDDQ)
±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current to GND or VDDQ
±100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θJA (see Note 3): DGG package
89
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range Tstg
–
65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.



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