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LDS8868 Datasheet(PDF) 9 Page - IXYS Corporation |
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LDS8868 Datasheet(HTML) 9 Page - IXYS Corporation |
9 / 14 page ![]() LDS8868 © 2009 IXYS Corp. 9 Doc. No. 8868_DS, Rev. N2.1 Characteristics subject to change without notice BLOCK DIAGRAM Figure 2. LDS8868 Functional Block Diagram BASIC OPERATION At power-up, EN pin should be logic LOW. During power-up device performs internal circuits reset that requires less than 10µs. To start device, EN pin should be set logic HIGH at least 10µs after VIN applied. Device starts operating at 1x mode at which the VOUT is approximately equal to VIN (less any internal voltage losses). If the output voltage is sufficient to regulate all LED currents, the device remains in 1x operating mode. . The low dropout PowerLite ™ Current regulator (PCR) performs well at input voltages up to 75 mV above LED forward voltage VF significantly increasing driver’s efficiency. The LDS8868 monitors voltage drop Vd across PCR at every channel in ON state. If this voltage falls below 75 mV (typical) at any one channel, (channel with LED with highest forward voltage), the Mode Control Block changes charge pump mode to the next multiplication ratio. Vd (LEDX1/2) = VIN x M – VF – Rcp x Iout, where Rcp is a Charge Pump Output Resistance at given mode, Iout is sum of all LED currents, and M is a charge pump’ multiplication ratio. If the input voltage is insufficient or falls to a level where Vd ≤75 mV, and the regulated currents cannot be maintained, the low dropout PowerLite ™ Current Regulator switches the charge pump into 1.5x mode (after a fixed delay time of about 800μs). In 1.5x mode, the charge pump’ output voltage is approximately equal to 1.5 times the input supply voltage (less any internal voltage losses). This sequence repeats until driver enters the 2x mode. LED Current Setting The current in each of the six LED channels is programmed through the 1-wire EN/SET digital |
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