DSP56857 datasheet(226/662 Pages) FREESCALE

226 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

9-8

Freescale Semiconductor

9.6 Register Descriptions (DMA_BASES = $1FFEC0, $1FFEC8,

$1FFED0, $1FFED8, $1FFEE0, $1FFEE8)

9.6.1 DMA Transfer Control (DMATC)

Figure 9-3. DMA Transfer Control (DMATC)

See Programmer’s Sheet on Appendix page B - 51

9.6.1.1 Direct Memory Access On (DMAON)—Bit 15

This bit enables/disables DMA operation. When the Circular Queue operation is disabled and the

DMACQS register is zero, this bit is automatically cleared at the conclusion of a DMA block

transfer or when the Transfer Count register decrements to zero.

•

0 = DMA Operation is disabled

•

1 = DMA Operation is enabled

9.6.1.2 Interrupt On (INTRON)—Bit 14

This bit enables/disables DMA interrupt operation. If DMA interrupt operation is enabled, the

DMA controller issues an interrupt whenever the DMA Transfer Count Register (DMACNT)

decrements to zero.

•

0 = DMA Interrupt Operation is disabled

•

1 = DMA Interrupt Operation is enabled

9.6.1.3 Interrupt Pending (INTRPEND)—Bit 13

This bit is the DMA Interrupt Pending bit. When this bit is asserted, a DMA interrupt is pending;

when this bit is deasserted, no DMA interrupt is pending.

•

0 = A DMA Interrupt is not pending

•

1 = A DMA Interrupt is pending

9.6.1.4 Data Size (DATASIZE)—Bit 12

This bit defines the data size of the DMA transfers and determines whether the DMA address

registers point to words or bytes.

•

0 = DMA transfers are performed in bytes (8 bits), with address registers pointing to bytes.

•

1 = DMA transfers are performed in words (16 bits), with address registers pointing to

words.

Base + $0

Read

DMAON INTRON

INTR_PEND

DATA_ SIZE

PERIPH SEL

SS/M

DS/M

Write

Reset

000

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