DSP56857 datasheet(380/662 Pages) FREESCALE

380 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

13-14

Freescale Semiconductor

13.9.2 Timer Channel Status and Control Registers (SCR)

There are four Timer Status and Control Registers in this occurrence. Their addresses are:

TMRA0_SCR (Timer A, Channel 0 Status and Control)—Address: TMRA_BASE + $7

TMRA1_SCR (Timer A, Channel 1 Status and Control)—Address: TMRA_BASE + $F

TMRA2_SCR (Timer A, Channel 2 Status and Control)—Address: TMRA_BASE + $17

TMRA3_SCR (Timer A, Channel 3 Status and Control)—Address: TMRA_BASE + $1F

Figure 13-5. TMR Status and Control Register (SCR)

See Programmer’s Sheet on Appendix page B - 93

13.9.2.1 Timer Compare Flag (TCF)—Bit 15

This bit is set when a successful compare occurs. Clear the bit by writing 0 to it.

13.9.2.2 Timer Compare Flag Interrupt Enable (TCFIE)—Bit 14

When set, this bit enables interrupts when the TCF bit is set.

13.9.2.3 Timer Overflow Flag (TOF)—Bit 13

This bit is set when the counter rolls over its maximum value $FFFF or $0000, depending on

count direction. Clear the bit by writing 0 to it.

13.9.2.4 Timer Overflow Flag Interrupt Enable (TOFIE)—Bit 12

When set, this bit enables interrupts when the TOF bit is set.

13.9.2.5 Input Edge Flag (IEF)—Bit 11

This bit is set when a positive input transition occurs while the counter is enabled. Clear the bit by

writing 0 to it.

Note:

Setting the Input Polarity Select (IPS) bit enables the detection of negative input edge

transitions detection. Also, the control register’s secondary count source determines

which external input pin is monitored by the detection circuitry.

13.9.2.6 Input Edge Flag Interrupt Enable (IEFIE)—Bit 10

When set, this bit enables interrupts when the IEF bit is set

Base + $7, $F,

$17, $1F

Read

TCF TCFIE TOF TOFIE

IEF

IEFIE IPS

INPUT

CAPTURE

MODE

MSTR EEOF VAL

OPS OEN

Write

FORCE

Reset

000

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