DSP56857 datasheet(194/662 Pages) FREESCALE

194 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

8-16

Freescale Semiconductor

8.7.5.7 ESSI1 Receive Data with Exception Status Interrupt Priority Level

(ESSI1_RDES IPL)—Bits 3–2

This bit field is used to set the interrupt priority levels for certain peripheral IRQs. These IRQs

are limited to priorities zero through two and are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

8.7.5.8 ESSI0 Transmit Last Slot Interrupt Priority Level

(ESSI0_TLS IPL)—Bits 1–0

This bit field is used to set the interrupt priority levels for certain peripheral IRQs. These IRQs

are limited to priorities zero through two and are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

8.7.6 Interrupt Priority Register 5 (IPR5)

Figure 8-8. Interrupt Priority Register 5 (IPR5)

See Programmer’s Sheet on Appendix page B - 29

8.7.6.1 Host I/F Transmit Interrupt Priority Level

(HOST_XMIT IPL)—Bits 15–14

This bit field is used to set the interrupt priority levels for certain peripheral IRQs. These IRQs

are limited to priorities zero through two and are disabled by default.

Base + $5

Read

HOST_XMIT

IPL

HOST_RCV

IPL

SCI0_RCV

IPL

SCI0_RERR

IPL

SCI0_RIDL

IPL

SCI0_TIDL

IPL

SCI0_XMIT

IPL

SPI_XMIT

IPL

Write

Reset

000

000000000

0000

DSP56857 Datasheet(PDF) 194 Page - Freescale Semiconductor, Inc

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