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AM5728 Datasheet(PDF) 109 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 109 Page - Texas Instruments |
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109 / 415 page ![]() 109 AM5729, AM5728, AM5726 www.ti.com SPRS953F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated 4.4 Signal Descriptions Many signals are available on multiple pins, according to the software configuration of the pin multiplexing options. Texas Instruments has developed an application called Pin Mux Utility that helps a system designer select the appropriate pin-multiplexing configuration for their device-based product design. The Pin Mux Utility provides a way to select valid IO Sets of specific peripheral interfaces to ensure the pinmultiplexing configuration selected for a design only uses valid IO Sets supported by the device. 1. SIGNAL NAME: The name of the signal passing through the pin. NOTE The subsystem multiplexing signals are not described in Table 4-2 and Table 4-3. 2. DESCRIPTION: Description of the signal 3. TYPE: Signal direction and type: – I = Input – O = Output – IO = Input or output – D = Open Drain – DS = Differential – A = Analog – PWR = Power – GND = Ground 4. BALL: Associated ball(s) bottom NOTE For more information, see the Control Module / Control Module Register Manual section of the device TRM. 4.4.1 Video Input Port (VIP) CAUTION The I/O timings provided in Section 7, Timing Requirements and Switching Characteristics are applicable for all combinations of signals for vin1, vin5 and vin6. However, the timings are valid only for vin2, vin3, and vin4 if signals within a single IOSET are used. The IOSETs are defined in the Table 7-4. NOTE For more information, see the Video Input Port (VIP) section of the device TRM. Table 4-4. VIP Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL Video Input 1 vin1a_clk0 Video Input 1 Port A Clock input. Input clock for 8-bit 16-bit or 24-bit Port A video capture. Input data is sampled on the CLK0 edge. I AG8 vin1a_de0 Video Input 1 Data Enable input I AD9 vin1a_fld0 Video Input 1 Port A Field ID input I AF9 |
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