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56F8167 Datasheet(PDF) 105 Page - Freescale Semiconductor, Inc |
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56F8167 Datasheet(HTML) 105 Page - Freescale Semiconductor, Inc |
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105 / 184 page ![]() Register Descriptions 56F8367 Technical Data, Rev. 7.0 Freescale Semiconductor 105 Preliminary 5.6.18.1 IRQ Pending (PENDING)—Bits 16–2 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number 5.6.18.2 Reserved—Bit 0 This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.19 IRQ Pending 1 Register (IRQP1) Figure 5-21 IRQ Pending 1 Register (IRQP1) 5.6.19.1 IRQ Pending (PENDING)—Bits 32–17 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number 5.6.20 IRQ Pending 2 Register (IRQP2) Figure 5-22 IRQ Pending 2 Register (IRQP2) 5.6.20.1 IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • 0 = IRQ pending for this vector number • 1 = No IRQ pending for this vector number $Base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING [32:17] Write RESET 11111 1111111 1111 Base + $13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING [48:33] Write RESET 11111 1111111 1111 |
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