56F8167 datasheet(179/184 Pages) FREESCALE

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Power Distribution and I/O Ring Implementation

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

179

Preliminary

•

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.

This is especially critical in systems with higher capacitive loads that could create higher transient currents

in the VDD and VSS circuits.

•

Take special care to minimize noise levels on the VREF, VDDA and VSSA pins

•

Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as development or

debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means

to assert TRST independently of RESET. Designs that do not require debugging functionality, such as

consumer products, should tie these pins together.

•

Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an

interface to this port to allow in-circuit Flash programming

12.3 Power Distribution and I/O Ring Implementation

Figure 12-1 illustrates the general power control incorporated in the 56F8367/56F8167. This chip

contains two internal power regulators. One of them is powered from the VDDA_OSC_PLL pin and cannot

be turned off. This regulator controls power to the internal clock generation circuitry. The other regulator

is powered from the VDD_IO pins and provides power to all of the internal digital logic of the core, all

peripherals and the internal memories. This regulator can be turned off, if an external VDD_CORE voltage

is externally applied to the VCAP pins.

In summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is

enabled. If the regulator is not enabled, a dual supply 3.3V/2.5V configuration can also be used.

Notes:

•

Flash, RAM and internal logic are powered from the core regulator output

•VPP1 and VPP2 are not connected in the customer system

•

All circuitry, analog and digital, shares a common VSS bus

Figure 12-1 Power Management

REG

CORE

VCAP

I/O

ADC

VDD

VSS

REG

VDDA_OSC_PLL

OSC

VSSA_ADC

VDDA_ADC

VREFH

VREFP

VREFMID

VREFN

VREFLO

56F8167 Datasheet(PDF) 179 Page - Freescale Semiconductor, Inc

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