5

FN9182.1

March 10, 2005

Bias Current

-5.0

-

-2.0

µA

Clamp Voltage

(Note 4)

6.5

-

8.0

V

PULSE WIDTH MODULATOR

Minimum Duty Cycle

VERR < 0.6V

-

-

0

%

Maximum Duty Cycle (per half-cycle)

RTD = 2.00k

Ω, CT = 220pF

RTD = 2.00k

Ω, CT = 470pF

-

-

-

94

97

99

-

-

-

%

Zero Duty Cycle VERR Voltage

0.85

-

1.20

V

VERR to PWM Comparator Input Offset

0.7

0.8

0.9

V

VERR to PWM Comparator Input Gain

0.31

0.33

0.35

V/V

Common Mode (CM) Input Range

(Note 4)

0

-

V

ERROR AMPLIFIER

Input Common Mode (CM) Range

(Note 4)

0

-

VREF

V

GBWP

(Note 4)

5

-

-

MHz

VERR VOL

-

-

0.4

V

VERR VOH

4.20

-

-

V

VERR Pull-Up Current Source

VERR = 2.5V

0.8

1.0

1.3

mA

EA Reference

0.594

0.600

0.606

V

EA Reference + EA Input Offset Voltage

0.590

0.600

0.612

V

OSCILLATOR

Frequency Accuracy, Overall

(Note 4)

165

183

201

kHz

-10

+10

%

Frequency Variation with VDD

-0.3

1.7

%

Temperature Stability

(Note 4)

-

-

4.5

1.5

-

-

%

Charge Current

-193

-200

-207

µA

Discharge Current Gain

19

20

23

µA/µA

CT Valley Voltage

Static Threshold

0.75

0.80

0.88

V

CT Peak Voltage

Static Threshold

2.75

2.80

2.88

V

CT Pk-Pk Voltage

Static Value

1.92

2.00

2.05

V

RTD Voltage

1.97

2.00

2.03

V

RESDEL Voltage Range

0

-

2

V

1.95

2.0

2.05

V/V

CTBUF Offset from GND

0.34

0.40

0.44

V

CTBUF VOH

-

-

0.10

V

CTBUF VOL

-

-

0.10

V

Electrical Specifications

Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic. 9 V < VDD< 20 V, RTD = 10.0k

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ISL6753