ST92195D7 datasheet(190/249 Pages) STMICROELECTRONICS

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ST92195C/D - TWO-CHANNEL I2C BUS INTERFACE (I2C)

I2C BUS INTERFACE (Cont’d)

FREQUENCY REGISTER (I2CFQR)

R241 - Read/Write

Reset Value: 0000 0000(00h)

Bits 7:6 = BUS_S[1:0]

I2C BUS Selection bits

These bits connect the I2C interface to one of the

two possible buses as described in Table 1.

Table 33. I2C bus selection

Bit 5 = FMEN

Fast Mode Enable bit

This bit enables or disables the fast mode for the

SCL bus frequency.

0: Standard Mode (up to 100 kHz).

1: Fast Mode (over 100 kHz)

Bit 4 = PP_DRV

Push-Pull Drive mode bit

This bit determines if the master drives the SCL/

SDA buses in push-pull mode or in normal mode.

This allows the master to send data to the slave at

a faster speed.

0: The push-pull drive mode is disabled

1: The push-pull drive mode is enabled. All “nor-

mal” bus frequencies are doubled with the only

exception that the push-pull drive mode is auto-

matically disabled when Q[3:0]=1110 or

Q[3:0]=1111 to yield an SCL frequency of 500

kHz or 800 kHz. Refer to Q[3:0] bit description.

Note: The master automatically switches tempo-

rarily to normal bus driving mode with active pull-

up disabled and SCL frequency reduced by factor

of 2 when receiving acknowledges or data from

the addressed slave.

Bit 3:0 = Q[3:0]

SCL clock frequency bits

These bits select the SCL clock frequency when

the interface works in master mode. In slave trans-

mitter mode, they can be used to adjust the setting

up time between the first data byte and the clock.

Refer to Table 2.

In push-pull mode, the frequency values present-

ed in the following table correspond to an approxi-

mate frequency assuming that :

– the first data bit is transferred at a lower frequen-

cy (clock stretching capability),

– the acknowledge bit is transferred at the slave

speed without push-pull mode,

– other data bits are transferred with a real period

250 ns shorter than the values indicated in this

table.

Using the spike filter will add an internal delay act-

ing as a period increase by 250-ns steps.

Table 34. SCL Clock Frequency Selection

* These values are not covered by the Philips I2C

specification

Notes:

– The maximum allowed frequency depends on

the state of the FMEN control bit (If PP_DRV=0,

standard mode: 100 KHz; fast mode: 666.6 kHz)

– All frequency values depend on the bus line load

(except push-pull mode).

– All above values are obtained with loads corre-

sponding to a rise time from 0 to 250 ns.

– Any higher rise time (especially in standard

mode) will increase the period of the bus line fre-

quency by 250-ns steps.

BUS_S0 BUS_S1 FMEN PP_DRV

BUS_S1

BUS_S0

Selected Bus

SCL1/SDA1

SCL2/SDA2

SCL BUS FREQUENCY (in kHz)

Q[3:0]

PP_DRV = 0

SCL max Frequency

PP_DRV = 1

SCL Frequency (kHz)

(period: +0/-250ns

0000

20.10

40.40

0001

30.53

61.54

0010

40.40

81.63

0011

50.63

102.56

0100

63.49

129.03

0101

72.73

148.15

0110

85.11

173.91

0111

102.56

210.53

1000

129.03

266.67

1001

173.91

363.64

1010

210.53

444.44

1011

266.67

444.44

1100

400.00

571.43

1101

444.44

666.67

1110

444.44*

666.67

1111

666.67*

666.67

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