XRT7250 datasheet(199/463 Pages) EXAR

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XRT7250

DS3/E3 FRAMER IC

áç

REV. 1.1.1

180

Setting this bit-field to “1” enables the Transmit Sec-

tion (at the Block Level) for Interrupt Generation.

Conversely, setting this bit-field to “0” disables the

Transmit Section for interrupt generation.

What does it mean for the Transmit Section Inter-

rupts to be enabled or disabled at the Block Lev-

el?

If the Transmit Section is disabled (for interrupt gener-

ation) at the Block Level, then ALL Transmit Section

interrupts are disabled, independent of the interrupt

enable/disable state of the source level interrupts.

If the Transmit Section is enabled (for interrupt gener-

ation) at the block level, then a given interrupt will be

enabled at the source level. Conversely, if the Trans-

mit Section is enabled (for interrupt generation) at the

Block level, then a given interrupt will still be disabled,

if it is disabled at the source level.

As mentioned earlier, the Transmit Section of the

XRT7250 Framer IC contains the following two inter-

rupts

• Completion of Transmission of FEAC Message

Interrupt.

• Completion of Transmission of LAPD Message

Interrupt.

The Enabling/Disabling and Servicing of each of

these interrupts is described below.

4.2.6.1.1

The Completion of Transmission of

FEAC Message Interrupt.

If the Transmit Section interrupts have been enabled

at the Block level, then the user can enable or disable

the Completion of Transmission of a FEAC Message

Interrupt by writing the appropriate value into Bit 4 (Tx

FEAC Interrupt Enable) within the Transmit DS3

FEAC Configuration & Status Register (Address =

0x31) as illustrated below.

Setting this bit-field to “1” enables the Completion of

Transmission of a FEAC Message Interrupt. Con-

versely, setting this bit-field to “0” disables this inter-

rupt.

4.2.6.1.2

Servicing the Completion of Trans-

mission of a FEAC Message Interrupt

As mentioned earlier, once the user commands the

Transmit FEAC Processor to begin its transmission of

a FEAC Message, it will do the following.

1. It will read in the six-bit contents of the Tx DS3

FEAC Register (Address = 0x32) and encapsu-

late these 6 bits into a 16-bit data structure.

2. The Transmit FEAC Processor will then begin to

transmit this 16-bit data structure (to the Remote

Terminal Equipment) repeatedly for 10 consecu-

tive times.

3. Upon completion of the 10th transmission, the

XRT7250 Framer IC will generate the Completion

of Transmission of a FEAC Message Interrupt to

the Microcontroller/Microprocessor. Once the

XRT7250 Framer IC generates this interrupt, it

will do the following.

• Assert the Interrupt Output pin (INT) by toggling it

"Low".

BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

RxDS3/E3

Interrupt

Enable

Not Used

TxDS3/E3

Interrupt

Enable

One Second

Interrupt

Enable

R/W

RORO

R/W

000

TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

Tx FEAC

Interrupt

Enable

TxFEAC

Interrupt

Status

TxFEAC

Enable

TxFEAC

Busy

R/W

RUR

R/W

000

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