XRT7250 datasheet(306/463 Pages) EXAR

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XRT7250

DS3/E3 FRAMER IC

REV. 1.1.1

287

5.3.1.2.2

HDB3 Decoding

The Transmit E3 LIU Interface block and the associat-

ed LIU embed and combine the data and clocking in-

formation into the line signal that is transmitted to the

remote terminal equipment. The remote terminal

equipment has the task of recovering this data and

timing information from the incoming E3 data stream.

Most clock and data recovery schemes rely on the

use of Phase-Locked-Loop technology. One of the

problems of using Phase-Locked-Loop (PLL) technol-

ogy for clock recovery is that it relies on transitions in

the line signal, in order to maintain lock with the in-

coming E3 data-stream. Therefore, these clock re-

covery scheme, are vulnerable to the occurrence of a

long stream of consecutive zeros (e.g., no transitions

in the line). This scenario can cause the PLL to lose

lock with the incoming E3 data, thereby causing the

clock and data recovery process of the receiver to fail.

Therefore, some approach is needed to insure that

such a long string of consecutive zeros can never

happen. One such technique is HDB3 (or High Den-

sity Bipolar -3) encoding.

In general the HDB3 line code behaves just like AMI

with the exception of the case when a long string of

consecutive zeros occurs on the line. Any 4 consecu-

tive zeros will be replaced with either a "000V" or a

"B00V" where "B" refers to a Bipolar pulse (e.g., a

pulse with a polarity that is compliant with the AMI

coding rule). And "V" refers to a Bipolar Violation

pulse (e.g., a pulse with a polarity that violates the al-

ternating polarity scheme of AMI.) The decision be-

tween inserting an "000V" or a "B00V" is made to in-

sure that an odd number of Bipolar (B) pulses exist

between any two Bipolar Violation (V) pulses. The

Receive E3 LIU Interface block, when operating with

the HDB3 Line Code is responsible for decoding the

HD-encoded data back into a unipolar (binary-for-

mat). For instance, if the Receive E3 LIU Interface

block detects a "000V" or a "B00V" pattern in the in-

coming pattern, the Receive E3 LIU Interface block

will replace it with four (4) consecutive zeros.

Figure 132 presents a timing diagram that illustrates

examples of HDB3 decoding.

5.3.1.2.3

Line Code Violations

The Receive E3 LIU Interface block will also check

the incoming E3 data stream for line code violations.

For example, when the Receive E3 LIU Interface

block detects a valid bipolar violation (e.g., in HDB3

line code), it will substitute four zeros into the binary

data stream. However, if the bipolar violation is in-

valid, then an LCV (Line Code Violation) is flagged

and the PMON LCV Event Count Register (Address =

0x50 and 0x51) will also be incremented. Additional-

ly, the LCV-One-Second Accumulation Registers (Ad-

dress = 0x6E and 0x6F) will be incremented. For ex-

ample: If the incoming E3 data is HDB3 encoded, the

Receive E3 LIU Interface block will also increment the

LCV One-Second Accumulation Register if three (or

more) consecutive zeros are received.

5.3.1.2.4

RxLineClk Clock Edge Selection

The incoming unipolar or bipolar data, applied to the

RxPOS and the RxNEG input pins are clocked into

the Receive E3 LIU Interface block via the RxLineClk

signal. The Framer IC allows the user to specify

which edge (e.g, rising or falling) of the RxLineClk

signal will sample and latch the signal at the RxPOS

and RxNEG input signals into the Framer IC. The us-

er can make this selection by writing the appropriate

data to bit 1 of the I/O Control Register, as depicted

below.

FIGURE 132. ILLUSTRATION OF TWO EXAMPLES OF HDB3 DECODING

Line Signal

RxNEG

RxPOS

Data

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