VSC7440 datasheet(185/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

168

If the new SIP is a multicast, it is replaced with an IP address from the IP address table

ANA_ACL::SWAP_SIP.

The IP address table (ANA_ACL::SWAP_SIP) used by some of the above mentioned modes is indexed

using VCAP IS2 action POLICE_IDX (VCAP IS2 action POLICE_ENA must be 0). The IP address table

can contain 32 IPv4 addresses or 8 IPv6 addresses.

When swapping IP addresses or replacing the source IP address, it is also possible to preset the IPv4

TTL or the IPv6 hop limit. This is enabled by VCAP IS2 action TTL_UPDATE_ENA. The new TTL value

for IPv4 frames is configured in ANA_ACL::SWAP_IP_CTRL.IP_SWAP_IP4_TTL_VAL and the new hop

limit value for IPv6 frames is configured in ANA_ACL::SWAP_IP_CTRL.IP_SWAP_IP4_TTL_VAL.

IPv4 and IPv6 TCP/UDP frames have the option to replace the source and destination port numbers with

new values. This is enabled through VCAP IS2 action TCP_UDP_ENA and new port numbers are

provided by VCAP IS2 action MATCH_ID and MATCH_ID_MASK.

The IPv4 header checksum is updated whenever required by above mentioned frame rewrites. The UDP

checksum is updated whenever required for IPv6 frames and cleared for IPv4 frames.

3.21.2.2 Routing in ANA_ACL

The following table lists the registers associated with routing capabilities in ANA_ACL.

If PTP and routing is to be supported concurrently, then some routing related frame rewrites must be

done in ANA_ACL instead of in the rewriter. This is enabled in

ANA_ACL::VCAP_S2_MISC_CTRL.ACL_RT_SEL or by setting VCAP IS2 action ACL_RT_MODE.

When enabled, the frame’s DMAC is changed to the next-hop MAC address specificed by ANA_L3 and

the rewriter is informed not to rewrite the DMAC. The following classification results used by the rewriter

are changed when routing in ANA_ACL:

•

The frame’s classified VID is set to the egress VID.

•

The frame’s classified VSI is optionally set to the egress router leg

(ANA_ACL::VCAP_S2_MISC_CTRL.ACL_RT_UPDATE_GEN_IDX_ERLEG_ENA) or the egress

VID (ANA_ACL::VCAP_S2_MISC_CTRL.ACL_RT_UPDATE_GEN_IDX_EVID_ENA)

In addition, ANA_L3 must be setup to change the source MAC address with the address belonging to the

egress router leg (ANA_L3::ROUTING_CFG.RT_SMAC_UPDATE_ENA). The IPv4 TTL or IPv6 hop limit

is still decremented by the rewriter.

3.21.2.3 PTP Delay_Req/Resp Processing

VCAP IS2 actions can trigger PTP Delay_Req/resp processing where an incoming Delay_Req frame is

terminated and a Delay_Resp frame is generated with appropriate PTP updates.

The following table lists the registers associated with PTP processing and rewriting capabilities in

ANA_ACL.

Table 106 •

ANA_ACL Routing Registers

Description

Replication

ANA_ACL::VCAP_S2_MISC_CTRL.ACL_RT_SEL

Enable routing related frame rewrites in

ANA_ACL

None

ANA_ACL::VCAP_S2_MISC_CTRL.ACL_RT_UPDATE_

GEN_IDX_ERLEG_ENA

Enable use of egress router leg as VSI in

rewriter.

None

ANA_ACL::VCAP_S2_MISC_CTRL.ACL_RT_UPDATE_

GEN_IDX_EVID_ENA

Enable use of egress VID as VSI in rewriter. None

Table 107 •

ANA_ACL PTP Processing and Rewriting Registers

Description

Replication

ANA_ACL:PORT:PTP_CFG

PTP time domain configuration and PTP

portNumber configuration used in portIdentity.

Per port

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