VSC7440 datasheet(213/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

196

The policer burst capacity can be specified with 4K granularity

(ANA_AC_POL:POL_PORT_CFG:POL_PORT_THRES_CFG_0.PORT_THRES0).

Policing of traffic destined for CPU port or ports can be controlled (in

ANA_AC_POL:POL_PORT_CTRL:POL_PORT_CFG.TRAFFIC_TYPE_MASK(7) = 0 and CPU bypass

mask in ANA_AC_POL:POL_PORT_CTRL:POL_PORT_CFG.CPU_QU_MASK).

Port policers can individually be configured to affect frames towards CPU ports

(ANA_AC_POL:POL_PORT_CTRL:POL_PORT_CFG.LIMIT_CPU_TRAFFIC_ENA) or front ports

(ANA_AC_POL:POL_PORT_CTRL:POL_PORT_CFG.LIMIT_NONCPU_TRAFFIC_ENA).

The port policers can be configured for either serial or parallel operation

(ANA_AC_POL::POL_ALL_CFG.PORT_POL_IN_PARALLEL_ENA):

•

Serial. The policers are checked one after another. If a policer is closed, the frame is discarded and

the subsequent policer buckets are not updated with the frame.

•

Parallel. The policers are working in parallel independently of each other. Each frame is added to a

policer bucket if the policer is open, otherwise the frame is discarded. A frame may be added to one

policer although another policer is closed.

The following parameters can also be configured per policer.

•

The leaky bucket calculation can be configured to include or exclude preamble, inter-frame gap and

an optional encapsulation (ANA_AC_POL:POL_PORT_CTRL:POL_PORT_GAP.GAP_VALUE).

•

Each policer can be configured to measure frame rates instead of bit rates

(ANA_AC_POL:POL_PORT_CTRL:POL_PORT_CFG.FRAME_RATE_ENA).

•

Traffic with DP level below a certain level can be configured to bypass the policers

(ANA_AC_POL:POL_PORT_CTRL:POL_PORT_CFG.DP_BYPASS_LVL).

By default, a policer discards frames (to the affected port type: CPU and/or front port or ports) while the

policer is closed. A discarded frame is not forwarded to any ports (including the CPU).

However, each port policer has the option to run in flow control where the policer instead of discarding

frames instructs the MAC to issue flow control pause frames

(ANA_AC_POL:POL_ALL_CFG:POL_PORT_FC_CFG.FC_ENA). When operating in Flow control mode

it is possible to specify a hysteresis, which controls when the policer can re-open after having closed

(ANA_AC_POL:POL_PORT_CFG:POL_PORT_THRES_CFG_1. PORT_THRES1). The current flow

control state is accessible (ANA_AC_POL:POL_ALL_CFG:POL_PORT_FC_CFG.FC_STATE).

Note: Flow control signaling out of ANA_AC must be enabled

(ANA_AC_POL::POL_ALL_CFG.PORT_FC_ENA).

To improve fairness between small and large frames being policed by the same policer a hysteresis can

be specified for drop mode (ANA_AC_POL:POL_PORT_CFG:

POL_PORT_THRES_CFG_1.PORT_THRES1), which controls when the policer can re-open after

having closed. By setting it to a value larger than the maximum transmission unit, it can be guaranteed

that when the policer opens again, all frames have the same chance of being accepted.

Port policers can be configured operate on logical ports instead of physical ports

(ANA_AC_POL::POL_ALL_CFG.LPORT_POLICE_ENA) and thereby allow policing of aggregated port

bandwidth.

Traffic dropped by a policer can be counted by the port statistic block.

The following port policer debug events are available.

•

Bypass of policer due to pipeline handling can be identified

(ANA_AC_POL:POL_ALL_CFG:POL_STICKY.POL_PORT_PT_BYPASS_STICKY).

•

Bypass of policer due to DP bypass level can be identified

(ANA_AC_POL:POL_ALL_CFG:POL_STICKY.POL_PORT_BYPASS_STICKY).

•

Dropping of traffic towards CPU due to policer can be identified

(ANA_AC_POL:POL_ALL_CFG:POL_STICKY.POL_PORT_DROP_CPU_STICKY).

•

Dropping of traffic towards front port due to policer can be identified

(ANA_AC_POL:POL_ALL_CFG:POL_STICKY.POL_PORT_DROP_FWD_STICKY).

•

Policers that are active but not closed can be identified per policer

(ANA_AC_POL:POL_ALL_CFG:POL_STICKY.POL_PORT_ACTIVE_STICKY).

VSC7440 Datasheet(PDF) 213 Page - Microsemi Corporation

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