VSC7440 datasheet(255/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

238

3.25.3.6 DTI Bandwidth

For 64 bytes frames, AFI can inject up to 10.5 Gbps at 156 MHz clock frequency and up to 3.25 Gbps at

52 MHz clock frequency for a single DTI flow or inject a total bandwidth, across all DTI flows, of up to

26 Gbps at 156 MHz and up to 8 Gbps at 52 MHz.

Higher injection bandwidths can be supported for frame sizes larger than 64 bytes.

Injections into ingress data path must be forwarded through VD1. For 64 bytes frames, the maximum

bandwidth through VD1 is 10.5 Gbps at 156 MHz and up to 3.25 Gbps at 52 MHz.

Note: Depending on port configuration, cell bus bandwidth may impose additional bandwidth limitations.

The bandwidth that a DTI is injecting into a queue must not exceed the bandwidth, that HSCH is

transmitting from the queue, because the port’s FRM_OUT_MAX will then be reached, possibly affecting

other DTIs injecting on the same port. For more information, see Port Parameters, page 245. The only

exception is if there is only one DTI injecting on the port, because there are no other DTIs that could be

affected.

3.25.3.7 DTI Sequence Processing Time

For high bandwidth DTI flows, the time it takes to process the delays and frames in a DTI sequence must

be taken into account:

•

Processing a frame entry with no succeeding delay entry takes 12 clock cycles.

•

Processing a frame entry with a succeeding delay entry takes 12 clock cycles.

•

Processing a delay entry, which does not succeed a frame entry takes 12 clock cycles.

For example, a sequence consisting of a frame entry followed by two delay entries will take 24 clock

cycles to process. If the frame is a 64-byte frame and the clock period is 4 ns, this will corresponds to a

maximum flow bandwidth of approximately 7 Gbps ((64 + 20) × 8 bits/(24 × 4 ns) = 7 Gbps), regardless

of the delay values configured for the two delays.

Although it takes 12 clock cycles to process a delay entry, it is valid to configure a delay entry with a

delay smaller than 12 clock cycles, because this will be compensated for when generating the delay

between later frames in the sequence. For more information, see Figure 73, page 236. For example, the

delay between the rightmost frame B and the succeeding frame A will be 150 + 12 clock cycles (instead

of 150 + 1). To compensate for this, however, the delay between the succeeding two frames A will be

150 – 11 clock cycles.

3.25.4

Timer Triggered Injection

For TTIs, frame injection is controlled by timers. To control the time between injections, configure the

following registers for each TTI:

•

TTI_TIMER.TICK_IDX. For each TTI, one of eight configurable timer ticks shown in the following

table must be chosen.

•

TTI_TIMER.TIMER_LEN. The number of timer ticks that must elapse between each injection.

That is, the period between each injection becomes tick_period × TIMER_LEN.

VSC7440 Datasheet(PDF) 255 Page - Microsemi Corporation

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