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VSC7440 Datasheet(PDF) 263 Page - Microsemi Corporation

Part # VSC7440
Description  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 Datasheet(HTML) 263 Page - Microsemi Corporation

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Functional Descriptions
VMDS-10492 VSC7440 Datasheet Revision 4.2
246
FRM_OUT_MAX+TTI_FRM_OUT_MAX. This ensures that TTI injection are still possible, even if a DTI
flow faster than the port speed has been configured.
If PFC is used in conjunction with automatic frame injection, then either all frames must be injected into
queues controlled by the same flow control priority, or all frames must be injected into queues that cannot
be stopped by PFC.
If EEE is used in conjunction with automatic frame injection, then all frames for that port must be injected
into queues with the same urgent configuration.
Setting FRM_OUT_MAX = 0 will stop all injections on port.
3.26
Rewriter
The switch core includes a rewriter (REW) that is common for all ports. The rewriter performs all frame
editing prior to frame transmission. Each frame can be handled multiple times by the rewriter
•
One time per destination port.
•
One time towards the mirror target port.
•
One time when copied or redirected to internal and/or external CPU.
•
One time when looped back to the analyzer.
All frames that are input to the rewriter can be modified by previous blocks of the frame processing flow.
The internal frame header informs the rewriter what ingress frame manipulations (popping) are
performed on any given frame. The same ingress frame manipulation is performed for each copy of a
frame, while the rewriter may perform per destination specific egress frame manipulations (pushing) to
the frame.
The rewriter is the final step in the frame processing flow of the device.
3.26.1
Rewriter Operation
The rewriter supports the following frame operations.
•
VLAN tag (802.1Q, 802.1ad) editing: tagging of frames and remapping of PCP and DEI.
•
L3 routing. SMAC/DMAC, VID and TTL modifications for IPv4 and IPv6.
•
Implement Precision Time Protocol (PTP) time stamping by interfacing to the PTP block.
•
Interfacing to the loopback block. Loopback frames to ANA based on VCAP_ES0 actions. Rewrite
MACs and IFH of looped frames.
•
DSCP remarking: rewriting the DSCP value in IPv4 and IPv6 frames based on classified DSCP
value.
•
Insert or update VSTAX headers.
•
Handling of both Rx and Tx mirror frames.
•
Padding of undersize frames to 64 bytes or 76 bytes.
•
Frame FCS update control.
•
Add preamble to all frames with an external port destination.
3.26.2
Supported Ports
The device operates with up to 11 physical ports, two loopback ports, and two DEVCPU extraction ports
as possible frame destinations. These frame destinations are addressed by the rewriter using the egress
port number.
Table 169 •
Port Parameters
Register
Field
Description
Replication
PORT_CFG
FRM_OUT_MAX
Maximum number of injections outstanding for the
port at-a-time.
Per port
PORT_CFG
FRM_RM_ONLY
Only allows frame removal injections. That is,
normal injections are not allowed.
Per port
TTI_PORT_FRM_OUT
TTI_FRM_OUT_MAX
Additional injections that can be outstanding before
affecting TTI injection.
Per port



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