VSC7511 datasheet(143/324 Pages) MICROSEMI

143 / 324 page

Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

128

Figure 39 •

Low Power Idle Operation

Energy Efficient Ethernet is enabled per port through DEV::EEE_CFG.EEE_ENA.

By default, the egress port is transmitting enqueued data. This is the active state. If none of the port’s

egress queues have enqueued data for the time specified in DEV::EEE_CFG.EEE_TIMER_HOLDOFF,

the egress port instructs the PCS to enter the EEE sleep state.

When data is enqueued in any of the port’s egress queues, a timer (DEV::EEE_CFG.EEE_TIMER_AGE)

is started. If one of the following conditions is met, the port enters the wake up state.

•

A queue specified as high priority (QSYS:PORT:EEE_CFG.EEE_FAST_QUEUES) has any data to

transmit.

•

The total number of frames in the port’s egress queues exceeds

QSYS::EEE_THRES.EEE_HIGH_FRAMES.

•

The total number of bytes in the port’s egress queues exceeds

QSYS::EEE_THRES.EEE_HIGH_FRAMES.

•

The time specified in DEV::EEE_CFG.EEE_TIMER_AGE has passed. PCS is instructed to wake up.

To ensure that PCS, PHY, and link partner are resynchronized after waking up; the egress port holds

back transmission of data until the time specified in DEV::EEE_CFG.EEE_TIMER_WAKEUP has

passed. After this time interval, the port resumes transmission of data.

The status bit DEV::EEE_CFG.PORT_LPI is set while the egress port holds back data due to LPI (from

the sleep state to the wake up state, both included).

3.12

Scheduler and Shapers

The following table lists the registers associated with the scheduler and egress shaper control.

Each egress port contains a two-level priority-fair egress scheduler. The first scheduler level towards the

egress port schedules between QoS classes while the second scheduler level towards the egress

queues schedules between the ingress ports.

An egress scheduler is constructed using 9 scheduler elements. Each scheduler elements has 12 inputs

and 1 output. It contains a scheduler, which can be strict or mixed with a round robin based scheduling

algorithm. The round robin based scheduling algorithm can either be frame-based round robin or byte-

based deficit weighted round robin. The output port of a scheduler elements contains a dual leaky bucket

shaper.

The following illustration provides an overview of the egress scheduling system for egress port 0.

Table 101 •

Scheduler and Egress Shaper Control Registers

Description

Replication

QSYS::SHAPER_CFG

Configuration of egress shaper’s rate and burst.

158

QSYS::SE_CFG

Configuration of the scheduling algorithm.

158

QSYS::SE_DWRR_CFG

Configuration of DWRR scheduler’s costs.

158

QSYS::SHAPER_STATE

Status of the shaper bucket.

158

Active

Low-Power Idle

Active

Quiet

VSC7511 Datasheet(PDF) 143 Page - Microsemi Corporation

VSC7511 Datasheet(HTML) 143 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL