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Z8523016PSC Datasheet(PDF) 111 Page - Zilog, Inc. |
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Z8523016PSC Datasheet(HTML) 111 Page - Zilog, Inc. |
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111 / 120 page  == (QKDQFHG6HULDO &RPPXQLFDWLRQV&RQWUROOHU 36 == (UUDWD RSHUDWH LQ5HFHLYH ,QWHUUXSWVRQ )LUVW &KDUDFWHU DQG 6SHFLDO &RQGLWLRQ LQVWHDGRI5HFHLYH ,QWHUUXSW RQ6SHFLDO&RQGLWLRQ 2QO\ In this mode, the Anti-Lock feature is not enabled. The FIFO is locked after the last character of a frame has been transferred, and the interrupt condition does not disappear until after an Error Reset command is issued to the ESCC. No Reset Highest IUS command can clear any IP bit. 'DLV\ &KDLQ± 7KLVZRUNDURXQG XVHV WKHIROORZLQJ WZR FRQGLWLRQV – 7KH(2) LQWHUUXSW LV WKHKLJKHVW SULRULW\ LQWHUUXSW LI RQO\ RQHFKDQQHO LV XVHG – &KDQQHO $ LVWKHRQO\ FKDQQHOLVVXLQJ LQWHUUXSWV If both conditions are satisfied, allowing nested interrupts can solve the problem. The processor servicing an interrupt on the daisy chain must be interruptible again from another interrupt of higher priority on that same daisy chain. 555HJLVWHU±7KLV ZRUNDURXQGLV DSSOLFDEOHLI WKH(2)LQWHUUXSW LVXVHG RQO\ WR QRWLI\ DQRWKHU SDUW RI WKHVRIWZDUHWKDW WKHUH KDV EHHQ DQRWKHU IUDPH UHFHLYHG – 5HDG55 DIWHU LVVXLQJWKH Reset IUS FRPPDQG – &KHFN ELW RI55 7KLVELW ZKHQVHW LQGLFDWHVWKDW WKH6'/& IUDPH ),)2 FRQWDLQVDYDOLGIUDPH $OWKRXJK RQH LQWHUUXSW PLJKW KDYH EHHQ ORVW ,3 UHVHW E\ WKH Reset IUS FRPPDQG ELW RI 55 DOZD\V LQGLFDWHV WKDW DW OHDVW RQH IUDPHLV DYDLODEOH LQWKHIUDPH),)2 ,IELW RI 55LV QRWLI\ WKH FRQFHUQHGSDUW RIWKH VRIWZDUH WKDW DW OHDVW RQHIUDPH LVDYDLODEOH LQ WKH IUDPH),)2 :KHQWKH6'/& ),)2 LVHQDEOHG DQG 5HFHLYH ,QWHUUXSWV RQ6SHFLDO&RQGLWLRQV 2QO\ LVVHOHFWHG VRIWZDUHFKHFNVWKDW WKHUH LVD 5HFHLYH &KDUDFWHU $YDLODEOH LQWHUUXSW ZKLFKLV JHQHUDWHGE\ '0$ UHDGLQJDQ(2)FKDUDFWHU DQG EHIRUH LVVX LQJWKH Reset Highest IUS FRPPDQG 2WKHUZLVH WKH (2)LQWHUUXSW FRQGLWLRQV DUH FOHDUHGE\ WKDW FRPPDQG )LJXUH LOOXVWUDWHVWKH SURFHGXUHIRU UHVHWWLQJKLJKHVW ,86 |
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