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EDBA164B4PR-1DATF-R Datasheet(PDF) 134 Page - Micron Technology

Part # EDBA164B4PR-1DATF-R
Description  216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Features
PDF  152 Pages
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

EDBA164B4PR-1DATF-R Datasheet(HTML) 134 Page - Micron Technology

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Table 91: AC Timing (Continued)
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Parameter
Symbol
Min/
Max
tCK
Min
Data Rate
Unit Notes
1066
933
800
667
533
400
333
DQS input low-level width
tDQSL
MIN
–
0.4
0.4
0.4
0.4
0.4
0.4
0.4
tCK
(avg)
DQS falling edge to CK setup time
tDSS
MIN
–
0.2
0.2
0.2
0.2
0.2
0.2
0.2
tCK
(avg)
DQS falling edge hold time from
CK
tDSH
MIN
–
0.2
0.2
0.2
0.2
0.2
0.2
0.2
tCK
(avg)
Write postamble
tWPST
MIN
–
0.4
0.4
0.4
0.4
0.4
0.4
0.4
tCK
(avg)
Write preamble
tWPRE
MIN
–
0.35
0.35
0.35
0.35
0.35
0.35
0.35
tCK
(avg)
CKE Input Parameters
CKE minimum pulse width (HIGH
and LOW pulse width)
tCKE
MIN
3
3
3
3
3
3
3
3
tCK
(avg)
CKE input setup time
tISCKE
MIN
–
0.25
0.25
0.25
0.25
0.25
0.25
0.25
tCK
(avg)
9
CKE input hold time
tIHCKE
MIN
–
0.25
0.25
0.25
0.25
0.25
0.25
0.25
tCK
(avg)
10
Command Address Input Parameters3
Address and control input setup
time ( Vref based )
tIS
MIN
–
220
250
290
370
460
600
740
ps
11
Address and control input hold
time ( Vref based )
tIH
MIN
–
220
250
290
370
460
600
740
ps
11
Address and control input pulse
width
tIPW
MIN
–
0.40
0.40
0.40
0.40
0.40
0.40
0.40
tCK
(avg)
Boot Parameters (10 MHz–55 MHz)12, 13, 14
Clock cycle time
tCKb
MAX
–
100
100
100
100
100
100
100
ns
MIN
–
18
181818181818
CKE input setup time
tISCKEb
MIN
–
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
CKE input hold time
tIHCKEb
MIN
–
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
Address and control input setup
time
tISb
MIN
–
1150
1150 1150 1150 1150 1150 1150
ps
Address and control input hold
time
tIHb
MIN
–
1150
1150 1150 1150 1150 1150 1150
ps
DQS output data access time from
CK_t/CK_c
tDQSCKb
MIN
–
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
MAX
–
10.0
10.0
10.0
10.0
10.0
10.0
10.0
Data strobe edge to output data
edge tDQSQb - 1.2
tDQSQb
MAX
–
1.2
1.2
1.2
1.2
1.2
1.2
1.2
ns
Data hold skew factor
tQHSb
MAX
–
1.2
1.2
1.2
1.2
1.2
1.2
1.2
ns
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
AC Timing
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
134
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.



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