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ADE7978/ADE7933/ADE7932/ADE7923

Data Sheet

Rev. D | Page 114 of 125

Table 47. MASK0 Register (Address 0xE50A)

Bits

Bit Name

Default Value

Description

AEHF

When this bit is set to 1, it enables an interrupt when Bit 30 changes in any of the total

active energy registers (AWATTHR, BWATTHR, or CWATTHR).

FAEHF

When this bit is set to 1, it enables an interrupt when Bit 30 changes in any of the

fundamental active energy registers (AFWATTHR, BFWATTHR, or CFWATTHR).

REHF

When this bit is set to 1, it enables an interrupt when Bit 30 changes in any of the total

reactive energy registers (AVARHR, BVARHR, or CVARHR).

FREHF

When this bit is set to 1, it enables an interrupt when Bit 30 changes in any of the

fundamental reactive energy registers (AFVARHR, BFVARHR, or CFVARHR).

VAEHF

When this bit is set to 1, it enables an interrupt when Bit 30 changes in any of the apparent

energy registers (AVAHR, BVAHR, or CVAHR).

LENERGY

When this bit is set to 1, it enables an interrupt at the end of an integration over the integer

number of half line cycles set in the LINECYC register (line cycle energy accumulation mode).

REVAPA

When this bit is set to 1, it enables an interrupt when the Phase A active power (total or

fundamental) identified by Bit 0 (REVAPSEL) in the MMODE register changes sign.

REVAPB

When this bit is set to 1, it enables an interrupt when the Phase B active power (total or

fundamental) identified by Bit 0 (REVAPSEL) in the MMODE register changes sign.

REVAPC

When this bit is set to 1, it enables an interrupt when the Phase C active power (total or

fundamental) identified by Bit 0 (REVAPSEL) in the MMODE register changes sign.

REVPSUM1

When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the

CF1 datapath changes sign.

REVRPA

When this bit is set to 1, it enables an interrupt when the Phase A reactive power (total or

fundamental) identified by Bit 1 (REVRPSEL) in the MMODE register changes sign.

REVRPB

When this bit is set to 1, it enables an interrupt when the Phase B reactive power (total or

fundamental) identified by Bit 1 (REVRPSEL) in the MMODE register changes sign.

REVRPC

When this bit is set to 1, it enables an interrupt when the Phase C reactive power (total or

fundamental) identified by Bit 1 (REVRPSEL) in the MMODE register changes sign.

REVPSUM2

When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the

CF2 datapath changes sign.

CF1

When this bit is set to 1, it enables an interrupt when a high to low transition occurs at the

CF1 pin; that is, an active low pulse is generated. The interrupt can be enabled even if the

CF1 output is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of

power used at the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register

(see Table 52).

CF2

When this bit is set to 1, it enables an interrupt when a high to low transition occurs at the

CF2 pin; that is, an active low pulse is generated. The interrupt can be enabled even if the

CF2 output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of

power used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register

(see Table 52).

CF3

When this bit is set to 1, it enables an interrupt when a high to low transition occurs at the

CF3 pin; that is, an active low pulse is generated. The interrupt can be enabled even if the

CF3 output is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of

power used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register

(see Table 52).

DREADY

When this bit is set to 1, it enables an interrupt when all periodical (8 kHz rate) DSP

computations finish.

REVPSUM3

When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the

CF3 datapath changes sign.

[31:19]

Reserved

0 0000 0000

0000

Reserved. These bits do not manage any functionality.

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