LTM4686BEVPBF datasheet(114/130 Pages) AD

114 / 130 page

LTM4686B

114

Rev. 0

For more information www.analog.com

APPENDIX C: PMBUS COMMAND DETAILS

If any of these bits are set, the MFR bit in the STATUS_WORD will be set.

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command. Exception: The fault log present bit can only be

cleared by issuing the MFR_FAULT_LOG_CLEAR command.

Any supported fault bit in this command will initiate an ALERT event.

This command has one data byte.

MFR_PADS

This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit

assignments of this command are as follows:

BIT ASSIGNED DIGITAL PIN

VDD33 OV Fault

VDD33 UV Fault

Reserved

ADC Values Invalid, Occurs During Start-Up

SYNC Output Disabled Due to External Clock

PowerGood1

PowerGood0

Device Driving RUN1 Low

Device Driving RUN0 Low

RUN1

RUN0

Device Driving GPIO1 Low

Device Driving GPIO0 Low

GPIO1

GPIO0

A 1 indicates the condition is true.

This read-only command has two data bytes.

MFR_COMMON

The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products.

BIT

MEANING

MODULE NOT DRIVING ALERT LOW

MODULE NOT BUSY

CALCULATIONS NOT PENDING

OUTPUT NOT IN TRANSITION

NVM Initialized

Reserved

SHARE_CLK Timeout

WP Pin Status

This read-only command has one data byte.

LTM4686BEVPBF Datasheet(PDF) 114 Page - Analog Devices

LTM4686BEVPBF Datasheet(HTML) 114 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL