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STM32F405 Datasheet(PDF) 133 Page - STMicroelectronics |
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STM32F405 Datasheet(HTML) 133 Page - STMicroelectronics |
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133 / 204 page  DS8626 Rev 9 133/203 STM32F405xx, STM32F407xx Electrical characteristics 5.3.20 CAN (controller area network) interface Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.21 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 14. Table 66. Dynamic characteristics: Ethernet MAC signals for MII(1) 1. Guaranteed by characterization. Symbol Parameter Min Typ Max Unit tsu(RXD) Receive data setup time 9 - ns tih(RXD) Receive data hold time 10 - tsu(DV) Data valid setup time 9 - tih(DV) Data valid hold time 8 - tsu(ER) Error setup time 6 - tih(ER) Error hold time 8 - td(TXEN) Transmit enable valid delay time 0 10 14 td(TXD) Transmit data valid delay time 0 10 15 Table 67. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply - 1.8(1) -3.6 V VREF+ Positive reference voltage - 1.8(1)(2)(3) -VDDA VREF− Negative reference voltage - - 0 - fADC ADC clock frequency VDDA = 1.8(1)(3) to 2.4 V 0.6 15 18 MHz VDDA = 2.4 to 3.6 V(3) 0.6 30 36 MHz fTRIG(4) External trigger frequency fADC = 30 MHz, 12-bit resolution - - 1764 kHz -- - 17 1/fADC VAIN Conversion voltage range(5) - 0 (VSSAor VREF- tied to ground) -VREF+ V RAIN(4) External input impedance See Equation 1 for details -- 50 κΩ RADC(4)(6) Sampling switch resistance - - - 6 κΩ CADC(4) Internal sample and hold capacitor -- 4 - pF |
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