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STM32F405 Datasheet(PDF) 151 Page - STMicroelectronics |
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STM32F405 Datasheet(HTML) 151 Page - STMicroelectronics |
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151 / 204 page  DS8626 Rev 9 151/203 STM32F405xx, STM32F407xx Electrical characteristics Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) 1. CL = 30 pF. 2. Guaranteed by characterization. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK –0.5 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 0 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 2 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0.5 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 3 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns |
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