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PIC16F15213 Datasheet(PDF) 142 Page - Microchip Technology

Part # PIC16F15213
Description  PIC16F15213/14/23/24/43/44 Low Pin Count Microcontrollers
PDF  439 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F15213 Datasheet(HTML) 142 Page - Microchip Technology

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17.3
Individual Pin Configuration
A rising edge detector and a falling edge detector are present for each PORT pin. To enable a pin to detect a rising
edge, the associated bit of the IOCxP register must be set. To enable a pin to detect a falling edge, the associated bit
of the IOCxN register must be set. A PORT pin can be configured to detect rising and falling edges simultaneously by
setting both associated bits of the IOCxP and IOCxN registers, respectively.
17.4
Interrupt Flags
The bits located in the IOCxF registers are status flags that correspond to the interrupt-on-change pins of each port.
If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and
an interrupt will be generated if the IOCIE bit is set. The IOCIF bit located in the corresponding Peripheral Interrupt
Request (PIRx) register, is all the IOCxF bits ORd together. The IOCIF bit is read-only. All of the IOCxF Status bits
must be cleared to clear the IOCIF bit.
17.5
Clearing Interrupt Flags
The individual status flags (IOCxF register bits) will be cleared by resetting them to zero. If another edge is detected
during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the
value actually being written.
To ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits
must be performed. The following sequence is an example of clearing an IOC interrupt flag using this method.
Example 17-1. Clearing Interrupt Flags (PORTA Example)
MOVLW
0xff
XORWF
IOCAF, W
ANDWF
IOCAF, F
17.6
Operation in Sleep
An interrupt-on-change event will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected
while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed out of Sleep.
17.7
Register Definitions: Interrupt-on-Change Control
PIC16F15213/14/23/24/43/44
IOC - Interrupt-on-Change
© 2020-2022 Microchip Technology Inc.
and its subsidiaries
Data Sheet
DS40002195E-page 142



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