DSPIC30F datasheet(144/248 Pages) MICROCHIP

144 / 248 page

dsPIC30F

DS70083G-page 142

Preliminary

 2004 Microchip Technology Inc.

18.5

DCI Module Operation During CPU

Sleep and Idle Modes

18.5.1

DCI MODULE OPERATION DURING

CPU SLEEP MODE

The DCI module has the ability to operate while in

Sleep mode and wake the CPU when the CSCK signal

is supplied by an external device (CSCKD = 1). The

DCI module will generate an asynchronous interrupt

when a DCI buffer transfer has completed and the CPU

is in Sleep mode.

18.5.2

DCI MODULE OPERATION DURING

CPU IDLE MODE

If the DCISIDL control bit is cleared (default), the mod-

ule will continue to operate normally even in Idle mode.

If the DCISIDL bit is set, the module will halt when Idle

mode is asserted.

18.6

AC-Link Mode Operation

The AC-Link protocol is a 256-bit frame with one 16-bit

data slot, followed by twelve 20-bit data slots. The DCI

module has two Operating modes for the AC-Link pro-

tocol. These Operating modes are selected by the

COFSM<1:0> control bits in the DCICON1 SFR. The

first AC-Link mode is called ‘16-bit AC-Link mode’ and

is selected by setting COFSM<1:0> = 10. The second

AC-Link mode is called ‘20-bit AC-Link mode’ and is

selected by setting COFSM<1:0> = 11.

18.6.1

16-BIT AC-LINK MODE

In the 16-bit AC-Link mode, data word lengths are

restricted to 16 bits. Note that this restriction only

affects the 20-bit data time slots of the AC-Link proto-

col. For received time slots, the incoming data is simply

truncated to 16 bits. For outgoing time slots, the 4 LS

bits of the data word are set to ‘0’ by the module. This

truncation of the time slots limits the A/D and DAC data

to 16 bits but permits proper data alignment in the

TXBUF and RXBUF registers. Each RXBUF and

TXBUF register will contain one data time slot value.

18.6.2

20-BIT AC-LINK MODE

The 20-bit AC-Link mode allows all bits in the data time

slots to be transmitted and received but does not main-

tain data alignment in the TXBUF and RXBUF

registers.

The 20-bit AC-Link mode functions similar to the Multi-

Channel mode of the DCI module, except for the duty

cycle of the frame synchronization signal. The AC-Link

frame synchronization signal should remain high for 16

CSCK cycles and should be low for the following

240 cycles.

The 20-bit mode treats each 256-bit AC-Link frame as

sixteen, 16-bit time slots. In the 20-bit AC-Link mode,

the module operates as if COFSG<3:0> = 1111 and

WS<3:0> = 1111. The data alignment for 20-bit data

slots is ignored. For example, an entire AC-Link data

frame can be transmitted and received in a packed

fashion by setting all bits in the TSCON and RSCON

SFRs. Since the total available buffer length is 64 bits,

it would take 4 consecutive interrupts to transfer the

AC-Link frame. The application software must keep

track of the current AC-Link frame segment.

18.7

I2S Mode Operation

The DCI module is configured for I2S mode by writing

a value of ‘01’ to the COFSM<1:0> control bits in the

DCICON1 SFR. When operating in the I2S mode, the

DCI module will generate frame synchronization sig-

nals with a 50% duty cycle. Each edge of the frame

synchronization signal marks the boundary of a new

data word transfer.

The user must also select the frame length and data

word size using the COFSG and WS control bits in the

DCICON2 SFR.

18.7.1

I2S FRAME AND DATA WORD

LENGTH SELECTION

The WS and COFSG control bits are set to produce the

period for one half of an I2S data frame. That is, the

frame length is the total number of CSCK cycles

required for a left or a right data word transfer.

The BLEN bits must be set for the desired buffer length.

Setting BLEN<1:0> = 01 will produce a CPU interrupt,

once per I2S frame.

18.7.2

I2S DATA JUSTIFICATION

As per the I2S specification, a data word transfer will, by

default, begin one CSCK cycle after a transition of the

WS signal. A ‘MS bit left justified’ option can be

selected using the DJST control bit in the DCICON2

SFR.

If DJST = 1, the I2S data transfers will be MS bit left jus-

tified. The MS bit of the data word will be presented on

the CSDO pin during the same CSCK cycle as the ris-

ing or falling edge of the COFS signal. The CSDO pin

is tri-stated after the data word has been sent.

DSPIC30F Datasheet(PDF) 144 Page - Microchip Technology

DSPIC30F Datasheet(HTML) 144 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL