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S5320 – PCI Match Maker: Electrical Characteristics

Revision 5.03 – June 14, 2006

AMCC Confidential and Proprietary

DS1656

145

Data Sheet

TIMING SPECIFICATION

PCI Clock Specification

Table 5 summarizes the A.C. characteristics for the PCI bus signals as they apply to the S5320. The figures after

Table 5 visually indicate the timing relationships.

Notes:

1. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the minimum peak-to-peak portion

of the clock waveform as shown in Figure 1.

2. Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF equivalent load.

3. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total current delivered through the com-

ponent pin is less than or equal to the leakage current specification.

4. See the timing measurement conditions in Figure 3.

Figure 1. PCI Clock Timing

Table 5. Functional Operation Range

(VCC = 3.3V ± 5%, 0°C to 70°C, 50 pF load on outputs for MAX, 0 pF load for MIN)

Symbol

Parameter

Min

Max

Units

Notes

Tcyc

Clock Time

CLK High Time

CLK Low Time

Rise Time (0.2

VCC to 0.6VCC load)

V/ns

Fall Time (0.6

VCC to 0.2VCC load)

V/ns

CLK to Signal Valid Delay (Bused Signals)

CLK to Signal Valid Delay (Point-to-Point Signals)

1,2

Float to Active Delay

Active to Float Delay

-28

Rising Edge Setup

Hold from PCI Clock Rising Edge

0.6V

0.2V

0.6V

0.2V

TCL

IH2

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