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MPC821 Datasheet(PDF) 206 Page - NXP Semiconductors

Part # MPC821
Description  Design Specification
PDF  242 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC821 Datasheet(HTML) 206 Page - NXP Semiconductors

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Support Information
30
MPC860TFADS Daughter Board Design Specification—Rev 0.1
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
34
VFLS0
I/O
IP_B0/IWP0/VFLS0. PCMCIA slot B Input Port 0 or Instruction
Watchpoint 0 or Visible history Flushes Status 0. For the MPC823
or MPC850 daughter boards, configured as IP_B0. For all other
daughter boards - configured as VFLS0. May be configured to
any alternate function. Indicates in conjunction with VFLS1, the
number of instructions flushed from the core’s history buffer.
Indicates also whether the MPC is in debug mode. If not using the
debug port, may be configured for alternate function.
35
GND
36
SPKROUT
I, X
KR~/IRQ4~/SPKROUT.
Kill
Reservation
input
or
Interrupt
Request 4 input or PCMCIA Speaker Output. Configured on the
FADS as SPKROUT. May be configured to alternate function.
37
GND
38
VFLS1
I/O
IP_B1/IWP1/VFLS1. PCMCIA slot B Input Port 1 or Instruction
Watchpoint 1 or Visible history Flushes Status 1. For the MPC823
or MPC850 daughter boards, configured as IP_B1. For all other
daughter boards - configured as VFLS0. May be configured.
Indicates in conjunction with VFLS1, the number of instructions
flushed from the core’s history buffer. Indicates also whether the
MPC is in debug mode. If not using the debug port, may be
configured for alternate function.
39
GND
40
41
42
VF1
-
IP_B5/LWP1/VF1. PCMCIA slot B Input Port 5 or Load/Store
Watch-Point 1 or Visible Instruction Queue Flushes Status 1.
For MPC823 or MPC850 configured as IP_B5, for all other
daughter boards configured as VF1. May be configured to any
alternate function as no use is done with it on the FADS.
43
GND
44
AT1
-
ALE_B/DSCK/AT1. Address Latch Enable for PCMCIA slot B or
Debug Serial Clock or Address Type 1. For MPC823 or MPC850
daughter boards configured as ALE_B for all other daughter
boards configured as AT1. Not used on the FADS. May be
configured to any alternate function.
45
GND
46
AT0
I
IP_B6/DSDI/AT0. Input Port B 6 or Debug Serial Data Input or
Address Type 0. Configured on the as AT0. May be used for
alternate function.
47
GND
48
POE_A~
I, L
In fact OP1 of the PCMCIA I/F. Enables address buffers towards
the PC-Card.
TABLE 5-10. PM2 Interconnect Signals
Pin No.
Signal Name
Attribute
Description
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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