MPC821 datasheet(139/242 Pages) NXP

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MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

A•3

U22 - Auxiliary Board Control

"******************************************************************************

"* In this file (5):

"* 1) The use of BCLOSE~ is removed. This due to the assignment

BCLOSE~ to GPL4A. In order of using of GPL4A bit in the upm to determine

data sampling edge, GPL4A may not be used as a GPL. Therefore DramBankXCs~

must envelope the cycle so that data buffers remain open throughout the

cycle.

"* 2) Removed CS support for flash configuration. I.e., FlashCs1~ will not be

asserted during hard reset. Flash configuration will be supported on

silicon next revisions.

data buffers will still open for flash configuration when hard reset

asserted and flash configuration option bit, asserted.

"* 3) Since Bclose~ is no longer available, the data buffers will open

asynchronously. I.e., driven directly by the various chip-selects.

to provide data hold (0) on write cycles to flash, CSNT bit in the OR

should be programmed active, while ACS == 00.

"******************************************************************************

"* In This file (6), A12 and A11 are removed from the flash selection equation

"* since they can select only a 1/2 Mbyte of flash rather then 2Mbyte selection

"* needed. Therefore, only one bank of 2 Mbyte flash may be used (MCM29F020).

"* The rest of the CS are driven high constantly.

"******************************************************************************

"* In this file (7):

"* - Pon Reset Out is removed. Pon Reset is driven directly to MPC.

"* - Modck0 becomes Modck2

"* - A9 and A10 replace A11 and A12 in flash bank selection

"* - Optional BufClose~ is removed.

"* - DramEn becomes active-low to support debug-station support changes.

"* - Added F_PD(1:3) to support SMART Flash SIMMs.

"* - Support for 32KHz crystal - renewed.

"******************************************************************************

"* In this file (8):

"* - Added protection against data contention for write cycles after

Flash read cycle. This is achieved using a state-machine which identifies

end of flash read and a chain of internal gates serving as a delay line.

This kind of solution guaranties a fixed delay over the data buffer enable

signal, that is, only after a flash read cycle.

"******************************************************************************

"* In this file (9):

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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