Microsemi

Integrated Products Division

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 5

Copyright

© 2000

Rev. 1.0b, 2005-03-03

LX1993

High Efficiency LED Driver

I N T E GRA T ED

PR ODUC T S

APPLI CATI ON I N FORMATI O N

The LX1993 is a PFM boost converter that is

optimized for driving a string of series connected LEDs. It

operates in a pseudo-hysteretic mode with a fixed switch

“off time” of 300ns. Converter switching is enabled as

decrease to a value less than the voltage at the VADJ pin.

comparator A1 activates the control logic. The control

logic activates the DRV output circuit that connects to the

gate of the internal FET. The output (i.e., SW) is switched

“on” (and remains “on”) until the inductor current ramps up

to the peak current level. This current level is set via the

comparator A2.

The LED load is powered from energy stored in the

output capacitor during the inductor charging cycle. Once

the peak inductor current value is achieved, the output is

turned off (off-time is typically 300ns) allowing a portion

of the energy stored in the inductor to be delivered to the

load (e.g., see Figure 6, channel 2). This causes the output

feedback circuit. The LX1993 continues to switch until the

voltage at the FB pin exceeds the control voltage at the ADJ

maximum adjust voltage by the maximum series LED

current. A minimum value of 15Ω is recommended for

⎥⎦

⎤

⎢⎣

⎡

=

LEDmax

ADJmax

I

V

R

SET

The application of an external voltage source at the

ADJ pin provides for output current adjustment over the

entire dimming range and the designer can select one of

two possible methods. The first option is to connect a

PWM logic signal to the ADJ pin (e.g., see Figure 1). The

LX1993 includes an internal 50pF capacitor to ground that

works with an external resistor to create a low-pass filter

(i.e., filter out the AC component of a pulse width

to adjust the reference voltage directly at the ADJ pin by

applying a DC voltage from 0.0 to 0.3V (e.g., see Figure

2). The adjustment voltage level is selectable (with limited

accuracy) by implementing the voltage divider created

between the external series resistor and the internal 2.5MΩ

resistor. Disabling the LX1993 is achieved by driving the

SHDN pin with a low-level logic signal thus reducing the

device power consumption to approximately 0.5µA (typ).

Setting the level of peak inductor current to approximately

2X the expected maximum DC input current will minimize

the inductor size, the input ripple current, and the output

ripple voltage. The designer is encouraged to use inductors

that will not saturate at the peak inductor current level. An

inductor value of 47µH is recommended. Choosing a lower

value emphasizes peak current overshoot while choosing a

higher value emphasizes output ripple voltage. The peak

switch current is defined using a resistor placed between the

()

CS

SCALE

D

IN

MIN

PEAK

R

I

t

L

V

I

I

+

+

=

⎟

⎠

⎞

⎜

⎝

⎛

value.

4.02KΩ using nominal values for all other parameters.

kΩ

44mA

0ns

5

8

47µ7

3.0V

197mA

I

PEAK

×

+

×

⎟

⎠

⎞

⎜

⎝

⎛

+

=

approximately 428mA.

Output voltage ripple is a function of the inductor value

converter regulation scheme. When the switch is first turned

on, the peak-to-peak voltage ripple is a function of the output

transition error (i.e., typically 10mV), and the output

overshoot (when the stored energy in the inductor is

delivered to the load at the end of the charging cycle).

Therefore the total ripple voltage is

The initial droop can be estimated as follows where the

0.5V value in the denominator is an estimate of the voltage

drop across the inductor and the FET RDS_ON: