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MC68340 Datasheet(PDF) 265 Page - Freescale Semiconductor, Inc |
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MC68340 Datasheet(HTML) 265 Page - Freescale Semiconductor, Inc |
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265 / 441 page  MOTOROLA MC68340 USER’S MANUAL 6- 15 the FCR, and the size in the CCR. When the complete operand is written, the DAR is incremented by 0, 1, 2, or 4, according to the increment and size information specified by the DAPI and DSIZE bits of the CCR, and the byte transfer count register (BTC) is decremented by the number of bytes transferred. If the BTC is equal to zero and there were no errors, the CSR DONE bit is set, and the DONE ≈ signal for the DMA handshake is asserted. The DMA control signals ( DACK ≈ and DONE≈) are asserted in the destination (write) cycle when the destination device makes a request. See Figures 6-11 and 6-12 for timing diagrams of dual-address write for external burst and cycle steal modes. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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