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S3C9442 Datasheet(PDF) 17 Page - Samsung semiconductor |
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S3C9442 Datasheet(HTML) 17 Page - Samsung semiconductor |
17 / 50 page ![]() S3C9442/C9444/F9444/C9452/C9454/F9454 SAM88RCRI INSTRUCTION SET 6-17 COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to "0". Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 60 R 4 61 IR Examples: Given: R1 = 07H and register 07H = 0F1H: COM R1 → R1 = 0F8H COM @R1 → R1 = 07H, register 07H = 0EH In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B). |
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