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ES9820Q Datasheet(PDF) 116 Page - ESS Technology,Inc |
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ES9820Q Datasheet(HTML) 116 Page - ESS Technology,Inc |
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116 / 117 page ![]() CONFIDENTIAL ADVANCE INFORMATION 0.3 ES9820 Product Datasheet ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 116 Revision History Current Version 0.3 Rev. Date Notes 0.1.2 November 16, 2020 Initial release 0.2 April 14, 2021 • Corrected pin 5 naming in QFN pinout DONE • Updated Register 63-66 • Added Note on THD compensation • Added Input Impedance and capacitance • Updated GPIO Audio Data configurations • Updated Performance data • Updated Recommended Operating Conditions • Added Register 12,13 TDM_LINE_SEL_CHx descriptions • Updated Package Drawing, removed ESS symbol • Added Clock Distribution section • Updated Power Consumption table • Added I2S Serial timing table • Updated ASP references • Corrected Register 228 with clip descriptions to register 229 • Updated Digital Path diagram to include I2S decoder • Added Clip detection section • Digital Output & Input Ports • Reserved Reg 105[1],122[1] • Updated Register 194 descriptions • Updated Register 35,36 Register descriptions • Added I2S decoder and Programmable delay section • Updated Register Overview I2C table • Updated Register 73 descriptions • Added Register Map • Added Power Up/Down Sequences • Updated recommended operating conditions • Added Pin 41 Package pad description to Pin list 0.2.2 May 10, 2021 • Updated Register 23 FS_PHASE description. Recommended to set to 7’d10 • Updated Register 11 [7] TDM_GPIO456 • Minor correction on first page 0.2.3 June 10, 2021 • Reserved register 73 0.3 October 13, 2021 • Added minimum MCLK frequency • Updated description for registers 192 & 193 • Added clock configuration tables • Added 2x mode to clock distribution diagram • Added reserved register note to top of register listings • Added note on connecting package pin to DGND • Major overall formatting changes |
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