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TMS320DM647 Datasheet(PDF) 143 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 143 Page - Texas Instruments |
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143 / 166 page  www.ti.com 15 14 13 13 13 13 13 13 13 12 12 11 10 10 9 A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data Out/Transmit) ACLKR/X (CLKRP = CLKXP = 0)(B) ACLKR/X (CLKRP = CLKXP = 1)(A) TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). Figure 6-41. McASP Output Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 143 |
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