56F8335 datasheet(144/160 Pages) FREESCALE

144 / 160 page

56F8335 Technical Data, Rev. 5

144

Freescale Semiconductor

Preliminary

10.13 Controller Area Network (CAN) Timing

Note: CAN is NOT available in the 56F8135 device.

Figure 10-17 Bus Wake Up Detection

10.14 JTAG Timing

Table 10-21 CAN Timing1

1. Parameters listed are guaranteed by design

Characteristic

Symbol

Min

Max

Unit

See Figure

Baud Rate

BRCAN

—

Mbps

—

Bus Wake Up detection

T WAKEUP

—

μs

10-17

Table 10-22 JTAG Timing

Characteristic

Symbol

Min

Max

Unit

See Figure

TCK frequency of operation

using EOnCE1

1. TCK frequency of operation must be less than 1/8 the processor rate.

fOP

SYS_CLK/8

MHz

10-18

TCK frequency of operation not

using EOnCE1

fOP

SYS_CLK/4

MHz

10-18

TCK clock pulse width

tPW

—

10-18

TMS, TDI data set-up time

tDS

5—

10-19

TMS, TDI data hold time

tDH

5—

10-19

TCK low to TDO data valid

tDV

—30

10-19

TCK low to TDO tri-state

tTS

—30

10-19

TRST assertion time

tTRST

2T2

2. T = processor clock period (nominally 1/60MHz)

—ns

10-20

T WAKEUP

CAN_RX

CAN receive

data pin

(Input)

56F8335 Datasheet(PDF) 144 Page - Freescale Semiconductor, Inc

56F8335 Datasheet(HTML) 144 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL