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S71PL129JC0 Datasheet(PDF) 151 Page - SPANSION |
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S71PL129JC0 Datasheet(HTML) 151 Page - SPANSION |
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151 / 153 page  October 28, 2005 S71PL129Jxx_00_A8 S71PL129JC0/S71PL129JB0/S71PL129JA0 149 Advance Informatio n Read/Write Timings Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (min) period for Standby mode from CE1# Low to High transition. Figure 72. Standby Entry Timing after Read or Write Notes: 1. The all address inputs must be High from Cycle #1 to #5. 2. The address key must confirm the format specified in page 134. If not, the operation and data are not guaranteed. 3. After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation. Figure 73. Power Down Program Timing (for 32M/64M Only) tCHOX CE1# OE# WE# Active (Read) Standby Active (Write) Standby tCHWX ADDRESS CE1# DQ*3 WE# tRC OE# LB#, UB# RDa MSB*1 MSB*1 MSB*1 MSB*1 MSB*1 Key*2 tWC tWC tWC tWC tRC tCP tCP tCP tCP tCP tCP*3 Cycle #1 Cycle #2 Cycle #3 Cycle #4 Cycle #5 Cycle #6 RDa RDa X X RDb |
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