PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

viii

10.1.107REGISTER 0XA5 (0X294): COPS VC CONTROL AND STATUS (RX/TXB = 1,

RX TABLE) ......................................................................................................223

10.1.108REGISTER 0XA5 (0X294): COPS VC CONTROL AND STATUS (RX/TXB = 0,

TX TABLE).......................................................................................................228

10.1.109REGISTER 0XA6 (0X298) : COPS VC PARAMETERS (RX/TXB = 0, TX TABLE)

........................................................................................................................231

10.1.110REGISTER 0XA7 (0X29C): COPS INDIRECT CONTROL..............................234

10.1.111REGISTER 0XA8 (0X2A0): COPS INDIRECT ADDRESS..............................236

10.1.112REGISTER 0XA9 (0X2A4): COPS INDIRECT DATA.......................................237

10.2

10.2. MICROPROCESSOR ONLY ACCESS REGISTERS...........................................238

10.2.1

REGISTER 0XC0: PCID MICROPROCESSOR CONTROL............................238

10.2.2

REGISTER 0XC1: PCID MICROPROCESSOR INTERRUPT STATUS...........238

10.2.3

REGISTER 0XC2: PCID MICROPROCESSOR INDIRECT CONTROL..........240

10.2.4

REGISTER 0XC3: PCID MICROPROCESSOR INDIRECT DATA LOW WORD242

10.2.5

REGISTER 0XC4: PCID MICROPROCESSOR INDIRECT DATA HIGH WORD

........................................................................................................................243

10.2.6

REGISTER 0XC5: PCID MICROPROCESSOR WRITE MAILBOX CONTROL244

10.2.7

REGISTER 0XC6: PCID MICROPROCESSOR WRITE MAILBOX DATA........246

10.2.8

REGISTER 0XC8: PCID MICROPROCESSOR READ MAILBOX CONTROL 247

10.2.9

REGISTER 0XC9: PCID MICROPROCESSOR READ MAILBOX DATA .........249

10.4

PCI HOST ONLY ACCESS REGISTERS ......................................................................250

10.4.1

REGISTER 0X300: PCID CONTROL..............................................................250

10.4.2

REGISTER 0X304: PCID INTERRUPT STATUS.............................................256

10.4.3

REGISTER 0X308: PCID INTERRUPT ENABLE............................................260

10.4.4

REGISTER 0X30C: PCID MAILBOX / MICROPROCESSOR INTERRUPT

STATUS / ENABLE..........................................................................................261

10.4.6

REGISTER 0X314: PCID RX PACKET DESCRIPTOR TABLE BASE .............263