RELEASED

PM7382 FREEDM-32P256

DATA SHEET

PMC-2010333

ISSUE 3

FRAME ENGINE AND DATA LINK MANAGER 32P256

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

viii

FIGURE 46 – BERT INPUT TIMING ...............................................................309

FIGURE 47 – TRANSMIT DATA & FRAME PULSE TIMING (2.048 MBPS

H-MVIP MODE)..................................................................................... 311

FIGURE 48 – TRANSMIT DATA & FRAME PULSE TIMING (8.192 MBPS

H-MVIP MODE).....................................................................................312

FIGURE 49 – TRANSMIT DATA TIMING (NON H-MVIP MODE) ....................312

FIGURE 50 – BERT OUTPUT TIMING ...........................................................313

FIGURE 51 – PCI INTERFACE TIMING .........................................................314

FIGURE 52 – JTAG PORT INTERFACE TIMING............................................315

FIGURE 53 – 329 PIN PLASTIC BALL GRID ARRAY (PBGA) .......................317