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ST72321 Datasheet(PDF) 23 Page - STMicroelectronics |
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ST72321 Datasheet(HTML) 23 Page - STMicroelectronics |
23 / 189 page ![]() ST72321 23/189 6 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. An overview is shown in Figure 11. For more details, refer to dedicated parametric section. Main features ■ Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator) ■ Reset Sequence Manager (RSM) ■ Multi-Oscillator Clock Management (MO) – 5 Crystal/Ceramic resonator oscillators – 1 Internal RC oscillator ■ System Integrity Management (SI) – Main supply Low voltage detection (LVD) – Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply or the EVD pin – Clock Security System (CSS) with Clock Filter and Backup Safe Oscillator (enabled by op- tion byte) 6.1 PHASE LOCKED LOOP If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2. Caution: The PLL is not recommended for appli- cations where timing accuracy is required. See “PLL Characteristics” on page 151. Figure 10. PLL Block Diagram Figure 11. Clock, Reset and Supply Block Diagram 0 1 PLL OPTION BIT PLL x 2 fOSC2 / 2 fOSC LOW VOLTAGE DETECTOR (LVD) fOSC2 AUXILIARY VOLTAGE DETECTOR (AVD) MULTI- OSCILLATOR (MO) OSC1 RESET VSS EVD VDD RESET SEQUENCE MANAGER (RSM) CLOCK FILTER SAFE OSC CLOCK SECURITY SYSTEM (CSS) OSC2 MAIN CLOCK CSS Interrupt Request AVD Interrupt Request CONTROLLER PLL SYSTEM INTEGRITY MANAGEMENT WATCHDOG SICSR TIMER (WDG) WITH REALTIME CLOCK (MCC/RTC) AVD AVD AVD LVD RF CSS IE IE CSS D WDG RF 0 1 fOSC fOSC2 (option) 0 S F fCPU |
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