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ST72321 Datasheet(PDF) 44 Page - STMicroelectronics |
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ST72321 Datasheet(HTML) 44 Page - STMicroelectronics |
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44 / 189 page  ST72321 44/189 POWER SAVING MODES (Cont’d) 8.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see section 10.2 on page 57 for more de- tails on the MCCSR register). The MCU can exit HALT mode on reception of ei- ther a specific interrupt (see Table 7, “Interrupt Mapping,” on page 37) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Fig- ure 30). When entering HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT” op- tion bit of the option byte. The HALT instruction when executed while the Watchdog system is en- abled, can generate a Watchdog RESET (see sec- tion 14.1 on page 175 for more details). Figure 29. HALT Timing Overview Figure 30. HALT Mode Flow-chart Notes: 1. WDGHALT is an option bit. See option byte sec- tion for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Re- fer to Table 7, “Interrupt Mapping,” on page 37 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC reg- ister are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. HALT RUN RUN 256 OR 4096 CPU CYCLE DELAY RESET OR INTERRUPT HALT INSTRUCTION FETCH VECTOR [MCCSR.OIE=0] HALT INSTRUCTION RESET INTERRUPT 3) Y N N Y CPU OSCILLATOR PERIPHERALS 2) I[1:0] BITS OFF OFF 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON OFF XX 4) ON CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON ON XX 4) ON 256 OR 4096 CPU CLOCK DELAY WATCHDOG ENABLE DISABLE WDGHALT 1) 0 WATCHDOG RESET 1 (MCCSR.OIE=0) CYCLE |
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Similar Description - ST72321_04 |
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