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ST72321 Datasheet(PDF) 46 Page - STMicroelectronics |
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ST72321 Datasheet(HTML) 46 Page - STMicroelectronics |
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46 / 189 page  ST72321 46/189 9 I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre- sponding register bits in the DDR and OR regis- ters: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not pro- vide this register refer to the I/O Port Implementa- tion section). The generic I/O block diagram is shown in Figure 31 9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external inter- rupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. Each external interrupt vector is linked to a dedi- cated group of I/O port pins (see pinout description and interrupt section). If several input pins are se- lected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed. The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified. 9.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writ- ing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR reg- ister returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status: 9.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip periph- eral, the I/O pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. DR Push-pull Open-drain 0VSS Vss 1VDD Floating |
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