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ADNS-5030 Datasheet(PDF) 9 Page - AVAGO TECHNOLOGIES LIMITED |
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ADNS-5030 Datasheet(HTML) 9 Page - AVAGO TECHNOLOGIES LIMITED |
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9 / 24 page  AC Electrical Specifications Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD = 3.3 V. Parameter Symbol MinimumTypical MaximumUnits Notes Reset Pulse Width tRESET 250 ns Active low Motion Delay after Reset tMOT-RST 50 ms From NRESET pull high to valid motion, assuming VDD and motion is present Forced Rest Enable tREST-EN 1 s From Rest Mode(RM) bits set to target rest mode Wake from Forced Rest tREST-DIS 1 s From Rest Mode(RM) bits cleared to valid motion Power Down tPD 50 ms From PD (when bit 1 of register 0x0d is set) to low current Wake from Power Down tWAKEUP 50 55 ms From PD inactive (when NRESET pin is asserted low to high or write 0x5a to register 0x3a) to valid motion MISO Rise Time tr-MISO 40 200 ns CL = 100pF MISO Fall Time tf-MISO 40 200 ns CL = 100pF MISO Delay after SCLK tDLY-MISO 120 ns From SCLK falling edge to MISO data valid, no load conditions MISO Hold Time thold-MISO 0.5 1/fSCLK µs Data held until next falling SCLK edge MOSI Hold Time thold-MOSI 200 ns Amount of time data is valid after SCLK rising edge MOSI Setup Time tsetup-MOSI 120 ns From data valid to SCLK rising edge SPI Time between Write tSWW 30 µs From rising SCLK for last bit of the first data byte, Commands to rising SCLK for last bit of the second data byte SPI Time between Write and tSWR 20 µs From rising SCLK for last bit of the first data byte, Read Commands to rising SCLK for last bit of the second address byte SPI Time between Read tSRW 250 ns From rising SCLK for last bit of the first data byte, to and Subsequent Commands tSRR falling SCLK for the first bit of the next address SPI Read Address-Data tSRAD 4 µs From rising SCLK for last bit of the address byte, Delay to falling SCLK for first bit of data being read NCS Inactive after Motion tBEXIT 250 ns Minimum NCS inactive time after motion burst before Burst next SPI usage NCS to SCLK Active tNCS-SCLK 120 ns From NCS falling edge to first SCLK rising edge SCLK to NCS Inactive tSCLK-NCS 120 ns From last SCLK rising edge to NCS rising edge, (for Read Operation) for valid MISO data transfer SCLK to NCS Inactive tSCLK-NCS 20 µs From last SCLK rising edge to NCS rising edge, (for Write Operation) for valid MOSI data transfer NCS to MISO high-Z tNCS-MISO 250 ns From NCS rising edge to MISO high-Z state Transient Supply Current IDDT 60 mA Max supply current during a VDD ramp from 0 to VDD Figure 9. Distance from lens reference plane to tracking surface (Z). 2.40 (0.094) Z = OBJECT SURFACE SENSOR LENS LENS REFERENCE PLANE |
Similar Part No. - ADNS-5030 |
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Similar Description - ADNS-5030 |
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