MPC8280 datasheet(326/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-18

Freescale Semiconductor

9.9.1.5.2

Error Reporting

Except for setting the detected-parity-error bit, all parity error reporting and response is controlled by the

parity-error-response bit (see Section 9.11.2.3, “PCI Bus Command Register”). If the

parity-error-response bit is cleared, the PCI bridge completes all transactions regardless of parity errors

(address or data). If the bit is set, the PCI bridge asserts PERR two clocks after the actual data transfer in

which a data parity error is detected, and keeps PERR asserted for one clock. The PCI bridge asserts PERR

when acting as an initiator during a read transaction or as a target involved in a write to system memory.

Figure 9-9 shows the possible assertion points for PERR if the PCI bridge detects a data parity error.

Figure 9-9. PCI Parity Operation

As an initiator, the PCI bridge attempts to complete the transaction on the PCI bus if a data parity error is

detected and sets the data-parity-reported bit in the configuration space status register. If a data parity error

occurs on a read transaction, the PCI bridge aborts the transaction internally. As a target, the PCI bridge

completes the transaction on the PCI bus even if a data parity error occurs. If parity error occurs during a

write to system memory, the transaction completes on the PCI bus but is aborted internally, insuring that

potentially corrupt data does not go to memory.

When the PCI bridge asserts SERR, it sets the signaled-system-error bit in the configuration space status

address parity error on SERR is conditioned on the parity-error-response bit being enabled in the command

system error is passed to the PCI bridge’s interrupt processing logic to assert MCP. Figure 9-9 shows where

the PCI bridge could detect an address parity error and assert SERR or where the PCI bridge, acting as an

initiator, checks for the assertion of SERR signaled by the target detecting an address parity error.

ADDR

PCI_CLK

AD[31:0]

PCI_C/BE[3:0]

FRAME

IRDY

DEVSEL

TRDY

PAR

PERR

SERR

DATA

ADDR

DATA

CMD

BEs

CMD

BEs

MPC8280 Datasheet(PDF) 326 Page - Freescale Semiconductor, Inc

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