MPC8280 datasheet(826/1386 Pages) FREESCALE

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Universal Serial Bus Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

27-10

Freescale Semiconductor

If USEP1[RTE] is 1, the USB host controller uses a transaction-level interface to communicate with the

user. Each transaction uses one TrBD as described in Section 27.6.4, “USB Transaction Buffer Descriptor

(TrBD) for Host.” The USB host controller generates the token based on the TOK field in the TrBD. For

SETUP and OUT transactions, the TrBD points to a single buffer containing the data packet to be

transmitted. For IN transactions, the TrBD points to a single buffer which is used for the receive data

packet.

Table 27-3. USB Tokens

Token

Description

OUT

Packet-Level Interface

Transaction-Level Interface

Transmission begins when the USB host

controller fetches a TxBD containing OUT token

and a data TxBD and loads them to the host

FIFO. The token and data are transmitted and a

handshake is expected.

If a handshake is not received within the

expected time interval, the USB controller clears

TxBD[R] of data BD, sets the TxBD[TO]

indication and generates a TXE1 interrupt.

When STALL or NAK is received within the

expected time interval, the USB controller clears

TxBD[R] of data BD, sets the TxBD[STALL] or

TXBD[NAK] indication and generates a TXE1

interrupt. When ACK is received within the

expected time interval, the USB controller clears

TxBD[R] of data BD, and generates an interrupt

if TxBD[I] = 1.No indication is set.

The token TxBD[R] is cleared right after the

OUT token transmission.

Transmission begins when the USB host controller

fetches a TrBD with the TOK field indicating an OUT

transaction. The token is generated and then the data

packet from the buffer is transmitted and a handshake

is expected.

If a handshake is not received within the expected time

interval, the USB controller clears TrBD[R], sets the

TrBD[TO] indication and generates a TXE1 interrupt.

When STALL or NAK is received within the expected

time interval, the USB controller clears TrBD[R], sets

the TrBD[STALL] or TrBD[NAK] indication and

generates a TXE1 interrupt. When ACK is received

within the expected time interval, the USB controller

clears TrBD[R], and generates a TXB interrupt if

TrBD[I] = 1.No indication is set.

USB Out Transaction

Token

Data

Handshake Received

by Function

Indication on TxBD/TrBD

OUT

Sent by host

None

ACK

None

NAK

STALL

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