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MPC8280 Datasheet(PDF) 113 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 113 Page - Freescale Semiconductor, Inc |
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113 / 1386 page  Overview MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 1-19 Serial throughput is enhanced by connecting one MPC8280 in master or slave mode (with system core enabled or disabled) to another MPC8280 in master mode with the core enabled. The core in MPC8280-A can access the memory on the local bus of MPC8280-B. 1.7.2.3 High-Performance System Microprocessor Figure 1-11 shows a configuration with a high-performance system microprocessor (MPC750). Figure 1-11. High-Performance System Microprocessor Configuration In this system, the G2_LE core internal is disabled and an external high-performance microprocessor is connected to the 60x bus. MPC750 32-Kbyte I cache 32-Kbyte D cache Backside Cache MPC8280 (slave) Local Bus SDRAM/SRAM/DRAM 60x Bus SDRAM/SRAM/DRAM ATM Connection Tables Communication Channels UTOPIA PHY 155 Mbps PHY ATM |
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