MPC8280 datasheet(1242/1386 Pages) FREESCALE

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Fast Ethernet Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

36-8

Freescale Semiconductor

When flow-control mode is enabled (FPSMRx[FCE]) and the receiver identifies a pause-flow control

frame sent to individual or broadcast addresses, transmission stops for the time specified in the control

frame. During this pause, only the out-of-sequence frame is sent. Normal transmission resumes after the

pause timer stops counting. If another pause-control frame is received during the pause, the period changes

to the new value received.

36.7

CAM Interface

The MPC8280 internal address recognition logic can be used in combination with an external CAM. When

using a CAM, the FCC must be in promiscuous mode (FPSMRx[PRO] = 1). See Section 36.12, “Ethernet

Address Recognition.”

The Ethernet controller writes two 32-bit accesses to the CAM and then reads the result in a 32-bit access.

If the high bit of the result is set, the frame is rejected; otherwise, the lower 16 bits are attached to the end

of the frame.

When an external CAM is used for address filtering, users can choose to either discard rejected frames

(FPSMR[ECM] = 0) or receive rejected frames and signal the CAM miss in the RxBD

(FPSMR[ECM] = 1).

NOTE

The bus atomicity mechanism for CAM accesses may not function correctly

when the CPM performs a DMA access to an external CAM device. This

only impacts systems in which multiple CPMs will access the CAM.

36.8

Ethernet Parameter RAM

For Ethernet mode, the protocol-specific area of the FCC parameter RAM is mapped as in Table 36-2.

Length/type

88-08

Control frame type

MAC opcode

00-01

Pause command

MAC parameter

up to

0xFFFE

Pause period measured in slot times, most-significant

octet first with a two time-slot resolution.

Note: Because the pause period has a resolution of two

time slots, the value programmed in this field is rounded

up to the nearest even number before being used, as

follows:

MAC Parameter ValuePause Period

none

1 or 2 2 x slot time

3 or 4 4 x slot time

……

Reserved

—

FCS

Frame check sequence (CRC)

Table 36-1. Flow Control Frame Structure (continued)

Size [Octets]

Description

Value

Comment

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