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MPC8280 Datasheet(PDF) 1358 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 1358 Page - Freescale Semiconductor, Inc |
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1358 / 1386 page ![]() MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-4 Freescale Semiconductor SPI receive buffer descriptor, 27-24 Buffer descriptors ATM controller receive, 31-67, 31-71 transmit, 31-66, 31-76 BISYNC mode, 23-12 definition, 32-22 fast communications controllers (FCCs) Fast Ethernet mode receive, 36-24 transmit, 36-27 HDLC mode receive, 37-9 transmit, 37-12 overview receive, 30-10 transmit, 30-10 GCI mode monitor channel, 28-33 HDLC mode, 22-8 I 2C controller receive, 40-12 transmit, 40-13 IDMA emulation auto buffer, 19-15 IDMA buffers, 19-23 multi-channel controllers (MCCs) receive, 29-42 transmit, 29-45 overview, 20-10, 32-37 serial management controllers (SMCs), 28-4 serial peripheral interface (SPI) receive, 39-14 transmit, 39-15 transparent mode serial communications controllers (SCCs), 24-9 serial management controllers (SMCs), 28-26 UART mode serial communications controllers (SCCs), 21-14 serial management controllers (SMCs), 28-13 Buffers BUFCMD, 11-42 Bus interface hierarchical bus interface example, 11-102 BxTx (byte-select signals), 11-75 Byte stuffing, 23-1 Byte-select signals, 11-75 C Cache units, 2-8 Cascaded mode, 18-3 CHAMR (channel mode register), 29-8 CHAMR (channel mode register, transparent mode), 29-13, 29-15 Chip-select assertion timing, 11-53 chip-select machine, 11-51 signals, 11-74 write enable deassertion timing, 11-54 clock control,, 10-6, 10-7 Clocks memory map, 3-9 overview, 10-1 clocks and power control PLL pins,, 10-5 PLL, low power, and reset control register,, 10-6, 10-7 system clock control,, 10-6 system PLL skew elimination,, 10-2 clocks and reset keys memory map,, 3-5 CMXFCR (CMX FCC clock route register), 16-13 CMXSCR (CMX SCC clock route register), 16-16 CMXSI1CR (CMX SI1 clock route register), 16-12 CMXSI2CR (CMX SI2 clock route register), 16-12 CMXSMR (CMX SMC clock route register), 16-19 CMXUAR (CMX UTOPIA address register), 16-7 Commands ATM TRANSMIT command, 31-92 fast communications controllers (FCCs) Ethernet mode receive commands, 36-13 transmit commands, 36-12 HDLC mode receive commands, 37-6 transmit commands, 37-5 I 2C controller, 40-11 IDMA emulation, 19-26 serial peripheral interface (SPI), 39-12 communication processor module features, 35-7 Communications processor (CP) block diagram, 14-7 execution from RAM, 14-9 features list, 14-4 memory map, 3-19 microcode execution from RAM, 14-9 microcode revision number, 14-12 peripheral interface, 14-8 RCCR, 14-10 REV_NUM, 14-12 RTSCR, 14-11 RTSR, 14-12 Communications processor module (CPM) ATM controller |
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