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UPSD3422 Datasheet(PDF) 126 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 126 Page - STMicroelectronics |
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126 / 293 page ![]() I2C interface uPSD34xx 126/293 Table 60. Number of I2C bus samples taken after 1-to-0 transition on SDA (START Condition) Table 61. Start condition hold time Note: 1 833KHz is maximum for uPSD34xx devices. Table 62 provides recommended settings for S1SETUP based on various combinations of fOSC and fSCL. Note that the “Total Sample Period” times in Table 61 on page 126 are typically slightly less than the minimum START condition hold time, tHLDSTA for a given I 2C bus speed. Important note: The SCL bit rate fSCL must first be determined by bits CR[2:0] in the SFR S1CON before a value is chosen for SMPL_SET[6:0] in the SFR S1SETUP. Contents of S1SETUP Resulting value for S1SETUP Resulting Number of Samples Taken After 1-to-0 on SDA Line SS_EN bit SMPL_SET[6:0] 0 XXXXXXXb 00h (default) 1 1 0000000b 80h 1 1 0000001b 81h 2 1 0000010b 82h 3 ... ... ... ... 1 0001011b 8Bh 12 1 0010111b 97h 24 ... ... ... ... 1 1111111b FFh 128 I2C Bus Speed Range of I2C Clock Speed (fSCL) Minimum START Condition Hold Time (tHLDSTA) Standard Up to 100KHz 4000ns Fast 101KHz to 400KHz 600ns High 401KHz to 833KHz(1) 160ns |
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