M7040N datasheet(130/159 Pages) STMICROELECTRONICS

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M7040N

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SRAM READ with a Table of Up to Eight Devices

The following explains the SRAM READ operation

completed through a table of up to eight devices

using the following parameters: TLSZ = 01. Figure

97, page 131 diagrams a block of eight devices.

The following assumes that SRAM access is suc-

cessfully achieved through M7040N Device 0. Fig-

ure 98, page 132 and Figure 99, page 133 show

timing diagrams for Device 0 and Device 7, re-

spectively.

– Cycle 1A: The host ASIC applies the READ In-

struction on the CMD[1:0] using CMDV = 1. The

DQ Bus supplies the address, with DQ[20:19]

set to '10' to select the SRAM address. The host

ASIC selects the device for which ID[4:0] match-

es the DQ[25:21] lines. During this cycle the

host ASIC also supplies SADR[23:21] on

CMD[8:6].

– Cycle 1B: The host ASIC continues to apply the

READ Instruction on the CMD[1:0] using

CMDV = 1. The DQ Bus supplies the address

with DQ[20:19] set to '10' to select the SRAM

address.

– Cycle 2: The host ASIC floats DQ[71:0] to a 3-

state condition.

– Cycle 3: The host ASIC keeps DQ[71:0] in a 3-

state condition.

– Cycle 4: Theselected devicestarts todrive

DQ[71:0].

– Cycle 5: The selected device continues to drive

DQ[71:0] and drives ACK from high-Z to low

– Cycle 6: The selected device drives the READ

address on SADR[23:0]. It also drives ACK

high, CE_L low, WE_L high, and ALE_L low.

– Cycle 7: The selected device drives CE_L,

ALE_L, WE_L, and the DQ Bus in a 3-state con-

dition. It continues to drive ACK low.

At the end of Cycle 7, the selected device floats

ACK in 3-state condition and a new command can

begin.

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