M7040N datasheet(140/159 Pages) STMICROELECTRONICS

140 / 159 page

M7040N

140/159

SRAM WRITE witha Table of UptoEight Devices

The following explains the SRAM WRITE opera-

tion done through a table(s) of up to eight devices

with the following parameters (TLSZ = 01). The di-

agram of such a table is shown in Figure 104,

page 141.

The following assumes that SRAM access is done

through M7040N Device 0. Figure 105, page 142

and Figure 106, page 143 show the timing dia-

gram for Device 0 and Device 7, respectively.

– Cycle 1A: The host ASIC applies the WRITE In-

struction on CMD[1:0] using CMDV = 1. The DQ

Bus supplies the address with DQ[20:19] set to

'10' to select the SRAM address. The host ASIC

selects the device for which the ID[4:0] matches

the DQ[25:21] lines. The host ASIC also sup-

plies SADR[23:21] on CMD[8:6] in this cycle.

Note: CMD[2] must be set to '0' for SRAM

WRITE because Burst WRITEs into the SRAM

are not supported.

– Cycle 1B: The host ASIC continues to apply the

WRITE InstructiononCMD[1:0] using CMDV =

1. The DQ Bus supplies the address with

DQ[20:19] set to '10' to select the SRAM ad-

dress.

Note: CMD[2] must be set to '0' for SRAM

WRITE because Burst WRITEs into the SRAM

are not supported.

– Cycle 2: The host ASIC continues to drive

DQ[71:0]. The data in this cycle is not used by

the M7040N device.

– Cycle 3: The host ASIC continues to drive

DQ[71:0]. The data in this cycle is not used by

the M7040N device.

At the end of cycle 3, a new command can begin.

The WRITE is a pipelined operation. The WRITE

Cycle appears at the SRAM Bus, however, with

the same latency as that of a SEARCH Instruction,

as measured from the second cycle of the WRITE

command.

M7040N Datasheet(PDF) 140 Page - STMicroelectronics

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