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ST72321BXXX-AUTO Datasheet(PDF) 58 Page - STMicroelectronics |
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ST72321BXXX-AUTO Datasheet(HTML) 58 Page - STMicroelectronics |
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58 / 247 page  Interrupts ST72321Bxxx-Auto 58/247 flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be serviced) will therefore be lost if the clear sequence is executed. 7.3 Interrupts and low power modes All interrupts allow the processor to exit the Wait low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the Halt modes (see column “Exit from Halt/Active Halt” in Table 19: Interrupt mapping). When several pending interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt with “exit from Halt mode” capability and it is selected through the same decision process shown in Figure 18. Note: If an interrupt that is not able to exit from Halt mode is pending with the highest priority when exiting Halt mode, this interrupt is serviced after the first one serviced. 7.4 Concurrent and nested management The following Figure 19 and Figure 20 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 20. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure. Figure 19. Concurrent interrupt management MAIN IT4 IT2 IT1 TRAP IT1 MAIN IT0 I1 SOFTWARE 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 RIM IT3 I0 10 PRIORITY LEVEL |
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